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soc/amd/cezanne: FSP: Add UPD entry for eDP tuning 

The FSP gets these values from the UPD and sets the internal values.

The document about eDP tuning is attached in issue tracker of this
ticket, at the issue tracker b/203061533#comment6.

BUG=b:203061533

Cq-Depend: chrome-internal:4303901
Change-Id: I9b85faac4f2fa1fb2c14bb85b615346d4379baac
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59918
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Huang <patrick.huang@amd.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Zheng Bao 2021-12-06 23:09:37 +08:00 committed by Felix Held
parent 2a404b599b
commit 8b54c0e04b
3 changed files with 31 additions and 1 deletions
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13
src/soc/amd/cezanne/chip.h
View File

@ -106,6 +106,19 @@ struct soc_amd_cezanne_config {
uint8_t usb_phy_custom;
struct usb_phy_config usb_phy;
/* eDP phy tuning settings */
uint8_t edp_phy_override;
/* bit vector of phy, bit0=1: DP0, bit1=1: DP1, bit2=1: DP2 bit3=1: DP3 */
uint8_t edp_physel;
struct {
uint8_t dp_vs_pemph_level;
uint8_t tx_eq_main;
uint8_t tx_eq_pre;
uint8_t tx_eq_post;
uint8_t tx_vboost_lvl;
} edp_tuningset;
};
#endif /* CEZANNE_CHIP_H */

10
src/soc/amd/cezanne/fsp_m_params.c
View File

@ -157,6 +157,16 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
mcfg->usb_phy = NULL;
}
if (config->edp_phy_override) {
mcfg->edp_phy_override = config->edp_phy_override;
mcfg->edp_physel = config->edp_physel;
mcfg->dp_vs_pemph_level = config->edp_tuningset.dp_vs_pemph_level;
mcfg->tx_eq_main = config->edp_tuningset.tx_eq_main;
mcfg->tx_eq_pre = config->edp_tuningset.tx_eq_pre;
mcfg->tx_eq_post = config->edp_tuningset.tx_eq_post;
mcfg->tx_vboost_lvl = config->edp_tuningset.tx_vboost_lvl;
}
fsp_fill_pcie_ddi_descriptors(mcfg);
fsp_assign_ioapic_upds(mcfg);
mb_pre_fspm();

9
src/vendorcode/amd/fsp/cezanne/FspmUpd.h
View File

@ -95,7 +95,14 @@ typedef struct __packed {
/** Offset 0x04D3**/ uint32_t telemetry_vddcrsocOffset;
/** Offset 0x04D7**/ uint8_t UnusedUpdSpace1;
/** Offset 0x04D8**/ struct usb_phy_config *usb_phy;
/** Offset 0x04DC**/ uint8_t UnusedUpdSpace2[292];
/** Offset 0x04DC**/ uint8_t edp_phy_override;
/** Offset 0x04DD**/ uint8_t edp_physel;
/** Offset 0x04DE**/ uint8_t dp_vs_pemph_level;
/** Offset 0x04DF**/ uint8_t tx_eq_main;
/** Offset 0x04E0**/ uint8_t tx_eq_pre;
/** Offset 0x04E1**/ uint8_t tx_eq_post;
/** Offset 0x04E2**/ uint8_t tx_vboost_lvl;
/** Offset 0x04E3**/ uint8_t UnusedUpdSpace2[285];
/** Offset 0x0600**/ uint16_t UpdTerminator;
} FSP_M_CONFIG;