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util/msrtool: Fix names from IA32_MCO_xx to IA32_MC0_xx 

Change-Id: I46cd986f4914b214156da49db37ecfa749386ce8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26268
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Kyösti Mälkki 2018-05-13 09:19:00 +03:00
parent fbf57596bb
commit 8b72aaf3f7
3 changed files with 9 additions and 9 deletions
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6
util/msrtool/intel_atom.c
View File

@ -176,13 +176,13 @@ const struct msrdef intel_atom_msrs[] = {
}}, }},
{ BITS_EOT } { BITS_EOT }
}}, }},
{0x400, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCO_CTL", "", { {0x400, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_CTL", "", {
{ BITS_EOT } { BITS_EOT }
}}, }},
{0x401, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCO_STATUS", "", { {0x401, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_STATUS", "", {
{ BITS_EOT } { BITS_EOT }
}}, }},
{0x402, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCO_ADDR", "", { {0x402, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_ADDR", "", {
{ BITS_EOT } { BITS_EOT }
}}, }},
{0x404, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_CTL", "", { {0x404, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_CTL", "", {

6
util/msrtool/intel_core2_later.c
View File

@ -1057,13 +1057,13 @@ const struct msrdef intel_core2_later_msrs[] = {
}}, }},
{ BITS_EOT } { BITS_EOT }
}}, }},
{0x400, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCO_CTL", "", { {0x400, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_CTL", "", {
{ BITS_EOT } { BITS_EOT }
}}, }},
{0x401, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCO_STATUS", "", { {0x401, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_STATUS", "", {
{ BITS_EOT } { BITS_EOT }
}}, }},
{0x402, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCO_ADDR", "", { {0x402, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_ADDR", "", {
{ BITS_EOT } { BITS_EOT }
}}, }},
{0x403, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_MISC", "", { {0x403, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_MISC", "", {

6
util/msrtool/intel_nehalem.c
View File

@ -1621,13 +1621,13 @@ const struct msrdef intel_nehalem_msrs[] = {
}}, }},
{ BITS_EOT } { BITS_EOT }
}}, }},
{0x400, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCO_CTL", "", { {0x400, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_CTL", "", {
{ BITS_EOT } { BITS_EOT }
}}, }},
{0x401, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCO_STATUS", "", { {0x401, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_STATUS", "", {
{ BITS_EOT } { BITS_EOT }
}}, }},
{0x402, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCO_ADDR", "", { {0x402, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_ADDR", "", {
{ BITS_EOT } { BITS_EOT }
}}, }},
{0x403, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_MISC", "", { {0x403, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_MISC", "", {