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/: Remove extra space after comma 

Change-Id: Ic64625bdaf8c4e9f8a5c1c22cece7f4070012da7
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69903
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Elyes Haouas 2022-11-22 17:36:02 +01:00 committed by Eric Lai
parent cc22607dbf
commit 8b8ada6fdb
10 changed files with 11 additions and 11 deletions
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2
src/arch/x86/pirq_routing.c
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@ -164,7 +164,7 @@ static void pirq_route_irqs(unsigned long addr)
} }
for (i = 0; i < CONFIG_MAX_PIRQ_LINKS; i++) for (i = 0; i < CONFIG_MAX_PIRQ_LINKS; i++)
printk(BIOS_DEBUG, "PIRQ%c: %d\n", i + 'A', pirq[i]); printk(BIOS_DEBUG, "PIRQ%c: %d\n", i + 'A', pirq[i]);
pirq_assign_irqs(pirq); pirq_assign_irqs(pirq);
} }

2
src/drivers/intel/gma/intel_ddi.c
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@ -48,7 +48,7 @@ static void intel_prepare_ddi_buffers(int port, int use_fdi_mode)
hsw_ddi_translations_fdi : hsw_ddi_translations_fdi :
hsw_ddi_translations_dp); hsw_ddi_translations_dp);
printk(BIOS_SPEW, "Initializing DDI buffers for port %d in %s mode\n", printk(BIOS_SPEW, "Initializing DDI buffers for port %d in %s mode\n",
port, port,
use_fdi_mode ? "FDI" : "DP"); use_fdi_mode ? "FDI" : "DP");

2
src/lib/selfboot.c
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@ -93,7 +93,7 @@ static int load_one_segment(uint8_t *dest,
break; break;
} }
default: default:
printk(BIOS_INFO, "CBFS: Unknown compression type %d\n", compression); printk(BIOS_INFO, "CBFS: Unknown compression type %d\n", compression);
return 0; return 0;
} }
/* Calculate middle after any changes to len. */ /* Calculate middle after any changes to len. */

2
src/security/vboot/secdata_tpm.c
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@ -15,7 +15,7 @@
#include <console/console.h> #include <console/console.h>
#define VBDEBUG(format, args...) \ #define VBDEBUG(format, args...) \
printk(BIOS_INFO, "%s():%d: " format, __func__, __LINE__, ## args) printk(BIOS_INFO, "%s():%d: " format, __func__, __LINE__, ## args)
#define RETURN_ON_FAILURE(tpm_cmd) do { \ #define RETURN_ON_FAILURE(tpm_cmd) do { \
uint32_t result_; \ uint32_t result_; \

2
src/soc/intel/broadwell/pch/pcie.c
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@ -295,7 +295,7 @@ static void root_port_commit_config(void)
if (dev->enabled) if (dev->enabled)
continue; continue;
printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev));
/* 8.2 Configuration of PCI Express Root Ports */ /* 8.2 Configuration of PCI Express Root Ports */
pci_or_config32(dev, 0x338, 1 << 26); pci_or_config32(dev, 0x338, 1 << 26);

2
src/soc/samsung/exynos5420/dp_lowlevel.c
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@ -229,7 +229,7 @@ unsigned int exynos_dp_set_analog_power_down(unsigned int block, u32 enable)
CH2_PD | CH3_PD); CH2_PD | CH3_PD);
break; break;
default: default:
printk(BIOS_ERR, "DP undefined block number : %d\n", block); printk(BIOS_ERR, "DP undefined block number : %d\n", block);
return -1; return -1;
} }

4
src/southbridge/intel/bd82x6x/pch.c
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@ -327,7 +327,7 @@ static void pch_pcie_enable(struct device *dev)
} }
if (!dev->enabled) { if (!dev->enabled) {
printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev));
/* /*
* PCIE Power Savings for PantherPoint and CougarPoint/B1+ * PCIE Power Savings for PantherPoint and CougarPoint/B1+
@ -408,7 +408,7 @@ void pch_enable(struct device *dev)
return pch_pcie_enable(dev); return pch_pcie_enable(dev);
if (!dev->enabled) { if (!dev->enabled) {
printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev));
/* Ensure memory, io, and bus master are all disabled */ /* Ensure memory, io, and bus master are all disabled */
pci_and_config16(dev, PCI_COMMAND, pci_and_config16(dev, PCI_COMMAND,

2
src/southbridge/intel/i82801gx/i82801gx.c
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@ -56,7 +56,7 @@ void i82801gx_enable(struct device *dev)
u16 reg16; u16 reg16;
if (!dev->enabled) { if (!dev->enabled) {
printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev));
/* Ensure memory, io, and bus master are all disabled */ /* Ensure memory, io, and bus master are all disabled */
reg16 = pci_read_config16(dev, PCI_COMMAND); reg16 = pci_read_config16(dev, PCI_COMMAND);

2
src/southbridge/intel/lynxpoint/pch.c
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@ -185,7 +185,7 @@ void pch_enable(struct device *dev)
return; return;
if (!dev->enabled) { if (!dev->enabled) {
printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev));
/* Ensure memory, io, and bus master are all disabled */ /* Ensure memory, io, and bus master are all disabled */
pci_and_config16(dev, PCI_COMMAND, pci_and_config16(dev, PCI_COMMAND,

2
src/southbridge/intel/lynxpoint/pcie.c
View File

@ -322,7 +322,7 @@ static void root_port_commit_config(void)
if (dev->enabled) if (dev->enabled)
continue; continue;
printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev));
/* Ensure memory, io, and bus master are all disabled */ /* Ensure memory, io, and bus master are all disabled */
pci_and_config16(dev, PCI_COMMAND, pci_and_config16(dev, PCI_COMMAND,