Random minor cosmetical or coding style fixes (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2966 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Uwe Hermann
parent
cc3ccdb643
commit
8b942e75d2
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@ -104,7 +104,6 @@ default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
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##
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default HAVE_PIRQ_TABLE=1
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default IRQ_SLOT_COUNT=5
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#object irq_tables.o
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##
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## Build code to export a CMOS option table
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@ -38,7 +38,7 @@
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#define POST_CODE(x) outb(x, 0x80)
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#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
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/* The alix1c has no SMBUS; the setup is hard-wired. */
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/* The ALIX1.C has no SMBus; the setup is hard-wired. */
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void cs5536_enable_smbus(void)
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{
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}
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@ -46,7 +46,8 @@ void cs5536_enable_smbus(void)
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#include "southbridge/amd/cs5536/cs5536_early_setup.c"
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#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
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/* the part is a hynix hy5du121622ctp-d43
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/* The part is a Hynix hy5du121622ctp-d43.
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*
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* HY 5D U 12 16 2 2 C <blank> T <blank> P D43
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* Hynix
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* DDR SDRAM (5D)
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@ -62,18 +63,17 @@ void cs5536_enable_smbus(void)
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* Lead Free (P)
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* DDR400 3-3-3 (D43)
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*/
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/* spd array */
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static u8 spdbytes[] = {
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/* SPD array */
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static const u8 spdbytes[] = {
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[SPD_ACCEPTABLE_CAS_LATENCIES] = 0x10,
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[SPD_BANK_DENSITY] = 0x40,
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[SPD_DEVICE_ATTRIBUTES_GENERAL] = 0xff,
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[SPD_MEMORY_TYPE] = 7,
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[SPD_MIN_CYCLE_TIME_AT_CAS_MAX] = 10, /* This is a guess for tRAC value */
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[SPD_MODULE_ATTRIBUTES] = 0xff, /* fix me later when we figure out */
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[SPD_MIN_CYCLE_TIME_AT_CAS_MAX] = 10, /* A guess for the tRAC value */
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[SPD_MODULE_ATTRIBUTES] = 0xff, /* FIXME later when we figure out. */
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[SPD_NUM_BANKS_PER_SDRAM] = 4,
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[SPD_PRIMARY_SDRAM_WIDTH] = 8,
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/* alix1c is 1 bank. */
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[SPD_NUM_DIMM_BANKS] = 1,
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[SPD_NUM_DIMM_BANKS] = 1, /* ALIX1.C is 1 bank. */
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[SPD_NUM_COLUMNS] = 0xa,
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[SPD_NUM_ROWS] = 3,
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[SPD_REFRESH] = 0x3a,
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@ -101,14 +101,17 @@ static u8 spd_read_byte(u8 device, u8 address)
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print_debug(" returns ");
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print_debug_hex8(spdbytes[address]);
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print_debug("\r\n");
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return spdbytes[address];
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}
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#define ManualConf 0 /* Do automatic strapped PLL config */
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#define PLLMSRhi 0x00001490 /* manual settings for the PLL */
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#define PLLMSRhi 0x00001490 /* Manual settings for the PLL */
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#define PLLMSRlo 0x02000030
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#define DIMM0 0xA0
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#define DIMM1 0xA2
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#define DIMM0 0xa0
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#define DIMM1 0xa2
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#include "northbridge/amd/lx/raminit.h"
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#include "northbridge/amd/lx/pll_reset.c"
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#include "northbridge/amd/lx/raminit.c"
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@ -119,6 +122,7 @@ static u8 spd_read_byte(u8 device, u8 address)
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static void msr_init(void)
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{
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msr_t msr;
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/* Setup access to the MC for under 1MB. Note MC not setup yet. */
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msr.hi = 0x24fffc02;
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msr.lo = 0x10010000;
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@ -131,12 +135,11 @@ static void msr_init(void)
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msr.hi = 0x20000000;
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msr.lo = 0xfff00;
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wrmsr(MSR_GLIU1 + 0x20, msr);
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}
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/** Early mainboard specific GPIO setup. */
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static void mb_gpio_init(void)
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{
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/* Early mainboard specific GPIO setup */
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}
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void cache_as_ram_main(void)
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@ -144,7 +147,9 @@ void cache_as_ram_main(void)
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static const struct mem_controller memctrl[] = {
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{.channel0 = {0x50}},
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};
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extern void RestartCAR();
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POST_CODE(0x01);
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SystemPreInit();
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@ -152,9 +157,8 @@ void cache_as_ram_main(void)
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cs5536_early_setup();
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/* NOTE: must do this AFTER the early_setup!
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* it is counting on some early MSR setup
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* for cs5536
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/* NOTE: Must do this AFTER cs5536_early_setup()!
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* It is counting on some early MSR setup for the CS5536.
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*/
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cs5536_disable_internal_uart();
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w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
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@ -169,10 +173,11 @@ void cache_as_ram_main(void)
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sdram_initialize(1, memctrl);
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/* Check memory */
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/* enable this only if you are having questions */
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/* ram_check(0x00000000, 640 * 1024);*/
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/* Enable this only if you are having questions. */
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/* ram_check(0, 640 * 1024); */
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/* Switch from Cache as RAM to real RAM
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/* Switch from Cache as RAM to real RAM.
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*
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* There are two ways we could think about this.
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*
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* 1. If we are using the auto.inc ROMCC way, the stack is
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@ -196,10 +201,10 @@ void cache_as_ram_main(void)
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print_err("POST 02\n");
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__asm__("wbinvd\n");
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print_err("Past wbinvd\n");
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/* we are finding the return does not work on this
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* board. Explicitly call the label that is after the call to
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* us. This is gross, but sometimes at this level it is the
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* only way out
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/* We are finding the return does not work on this board. Explicitly
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* call the label that is after the call to us. This is gross, but
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* sometimes at this level it is the only way out.
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*/
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done_cache_as_ram_main();
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}
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@ -20,7 +20,6 @@
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#include <arch/pirq_routing.h>
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#include <console/console.h>
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#include <arch/io.h>
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#include <arch/pirq_routing.h>
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#include "../../../southbridge/amd/cs5536/cs5536.h"
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/* Platform IRQs */
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@ -41,7 +40,11 @@
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#define L_PIRQC 3 /* Means Slot INTx# Connects To Chipset INTC# */
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#define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */
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/* ALIX 1c interrupt wiring. Devices are:
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/*
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* ALIX1.C interrupt wiring.
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*
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* Devices are:
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*
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* 00:01.0 Host bridge: Advanced Micro Devices [AMD] CS5536 [Geode companion] Host Bridge (rev 31)
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* 00:01.2 Entertainment encryption device: Advanced Micro Devices [AMD] Geode LX AES Security Block
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* 00:0d.0 Ethernet controller: VIA Technologies, Inc. VT6105M [Rhine-III] (rev 96)
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@ -51,8 +54,11 @@
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* 00:0f.3 Multimedia audio controller: Advanced Micro Devices [AMD] CS5536 [Geode companion] Audio (rev 01)
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* 00:0f.4 USB Controller: Advanced Micro Devices [AMD] CS5536 [Geode companion] OHC (rev 02)
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* 00:0f.5 USB Controller: Advanced Micro Devices [AMD] CS5536 [Geode companion] EHC (rev 02)
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*
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* The only devices that interrupt are:
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* What device IRQ PIN PIN WIRED TO
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*
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* What Device IRQ PIN PIN WIRED TO
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* -------------------------------------------------
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* AES 00:01.2 0a 01 A A
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* 3VPCI 00:0c.0 0a 01 A A
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* eth0 00:0d.0 0b 01 A B
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@ -61,12 +67,13 @@
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* usb 00:0f.4 0b 04 D D
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* usb 00:0f.5 0b 04 D D
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*
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* The only swizzled interrupt is eth0, where INTA is wired to interrupt controller line B
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* The only swizzled interrupt is eth0, where INTA is wired to interrupt controller line B.
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*/
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const struct irq_routing_table intel_irq_routing_table = {
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PIRQ_SIGNATURE, /* u32 signature */
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PIRQ_VERSION, /* u16 version */
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32 + 16 * IRQ_SLOT_COUNT,
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PIRQ_SIGNATURE,
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PIRQ_VERSION,
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32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
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0x00, /* Where the interrupt router lies (bus) */
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(0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */
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0x00, /* IRQs devoted exclusively to PCI usage */
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@ -74,26 +81,26 @@ PIRQ_VERSION, /* u16 version */
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0x002B, /* Device */
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0, /* Crap (miniport) */
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{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */
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0x00, /* u8 checksum , this has to set to
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* some value that would give 0
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* after the sum of all bytes
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* for this structure
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* (including checksum)
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*/
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0x00, /* Checksum */
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{
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/* If you change the number of entries,
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* change the IRQ_SLOT_COUNT above!
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*/
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/* If you change the number of entries, change IRQ_SLOT_COUNT above! */
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/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
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{0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* cpu */
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/* PCI SLOT */
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{0x00, (0x0C << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x4, 0x0}, /* slot1 */
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/* ONBOARD ETHER */
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{0x00, (0x0D << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* ethernet */
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/* MINI PCI */
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{0x00, (0x0E << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x1, 0x0}, /* mini slot2 */
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/* Chipset slots -- f.3 wires to B, and f.4 and f.5 wires to D */
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{0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */
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/* CPU */
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{0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},
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/* PCI (slot 1) */
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{0x00, (0x0C << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x4, 0x0},
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/* On-board ethernet */
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{0x00, (0x0D << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},
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/* Mini PCI (slot 2) */
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{0x00, (0x0E << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x1, 0x0},
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/* Chipset slots -- f.3 wires to B, and f.4 and f.5 wires to D. */
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{0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0},
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}
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};
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@ -21,14 +21,13 @@
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <device/pci_ops.h>
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#include <arch/io.h>
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#include <cpu/x86/msr.h>
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#include <cpu/amd/lxdef.h>
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#include "../../../southbridge/amd/cs5536/cs5536.h"
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#include "chip.h"
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/* Print the platform configuration */
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/* Print the platform configuration. */
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void print_conf(void) {
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#if DEFAULT_CONSOLE_LOGLEVEL >= BIOS_ERR
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int i;
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@ -156,8 +155,8 @@ void print_conf(void) {
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static void init(struct device *dev)
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{
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printk_debug("ALIX1C ENTER %s\n", __FUNCTION__);
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printk_debug("ALIX1C EXIT %s\n", __FUNCTION__);
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printk_debug("ALIX1.C ENTER %s\n", __FUNCTION__);
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printk_debug("ALIX1.C EXIT %s\n", __FUNCTION__);
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}
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static void enable_dev(struct device *dev)
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@ -4,19 +4,18 @@ mainboard pcengines/alix1c
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option CONFIG_COMPRESSED_PAYLOAD_NRV2B=0
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## ROM_SIZE is the total number of bytes allocated for LinuxBIOS use
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## (normal AND fallback images and payloads).
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## leave 36k for vsa
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##
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option ROM_SIZE = 512*1024 - 36 * 1024
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## (normal AND fallback images and payloads). Leave 36k for VSA.
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option ROM_SIZE = (512 * 1024) - (36 * 1024)
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## ROM_IMAGE_SIZE is the maximum number of bytes allowed for a LinuxBIOS image,
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## not including any payload.
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option ROM_IMAGE_SIZE=64*1024
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option ROM_IMAGE_SIZE = (64 * 1024)
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option FALLBACK_SIZE = ROM_SIZE
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option DEFAULT_CONSOLE_LOGLEVEL = 3
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option MAXIMUM_CONSOLE_LOGLEVEL = 11
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romimage "fallback"
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option USE_FALLBACK_IMAGE = 1
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option LINUXBIOS_EXTRA_VERSION = ".0Fallback"
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