AMD: Kconfig cleanup
Change-Id: Ie347b32575c26133d52c275622d29d1cd4c6c0c7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3623 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
This commit is contained in:
parent
3ad5a9b97f
commit
8b95c13420
|
@ -22,49 +22,43 @@ config CPU_AMD_AGESA_FAMILY12
|
|||
select PCI_IO_CFG_EXT
|
||||
select X86_AMD_FIXED_MTRRS
|
||||
|
||||
if CPU_AMD_AGESA_FAMILY12
|
||||
|
||||
config CPU_ADDR_BITS
|
||||
int
|
||||
default 48
|
||||
depends on CPU_AMD_AGESA_FAMILY12
|
||||
|
||||
config CPU_SOCKET_TYPE
|
||||
hex
|
||||
default 0x10
|
||||
depends on CPU_AMD_AGESA_FAMILY12
|
||||
|
||||
# DDR2 and REG
|
||||
config DIMM_SUPPORT
|
||||
hex
|
||||
default 0x0104
|
||||
depends on CPU_AMD_AGESA_FAMILY12
|
||||
|
||||
config EXT_RT_TBL_SUPPORT
|
||||
bool
|
||||
default n
|
||||
depends on CPU_AMD_AGESA_FAMILY12
|
||||
|
||||
config EXT_CONF_SUPPORT
|
||||
bool
|
||||
default n
|
||||
depends on CPU_AMD_AGESA_FAMILY12
|
||||
|
||||
config CBB
|
||||
hex
|
||||
default 0x0
|
||||
depends on CPU_AMD_AGESA_FAMILY12
|
||||
|
||||
config CDB
|
||||
hex
|
||||
default 0x18
|
||||
depends on CPU_AMD_AGESA_FAMILY12
|
||||
|
||||
config XIP_ROM_SIZE
|
||||
hex
|
||||
default 0x80000
|
||||
depends on CPU_AMD_AGESA_FAMILY12
|
||||
|
||||
config HAVE_INIT_TIMER
|
||||
bool
|
||||
default y
|
||||
depends on CPU_AMD_AGESA_FAMILY12
|
||||
|
||||
endif
|
||||
|
|
|
@ -22,54 +22,48 @@ config CPU_AMD_AGESA_FAMILY14
|
|||
select PCI_IO_CFG_EXT
|
||||
select X86_AMD_FIXED_MTRRS
|
||||
|
||||
if CPU_AMD_AGESA_FAMILY14
|
||||
|
||||
config CPU_ADDR_BITS
|
||||
int
|
||||
default 36
|
||||
depends on CPU_AMD_AGESA_FAMILY14
|
||||
|
||||
config CPU_SOCKET_TYPE
|
||||
hex
|
||||
default 0x10
|
||||
depends on CPU_AMD_AGESA_FAMILY14
|
||||
|
||||
# DDR2 and REG
|
||||
config DIMM_SUPPORT
|
||||
hex
|
||||
default 0x0104
|
||||
depends on CPU_AMD_AGESA_FAMILY14
|
||||
|
||||
config EXT_RT_TBL_SUPPORT
|
||||
bool
|
||||
default n
|
||||
depends on CPU_AMD_AGESA_FAMILY14
|
||||
|
||||
config EXT_CONF_SUPPORT
|
||||
bool
|
||||
default n
|
||||
depends on CPU_AMD_AGESA_FAMILY14
|
||||
|
||||
config CBB
|
||||
hex
|
||||
default 0x0
|
||||
depends on CPU_AMD_AGESA_FAMILY14
|
||||
|
||||
config CDB
|
||||
hex
|
||||
default 0x18
|
||||
depends on CPU_AMD_AGESA_FAMILY14
|
||||
|
||||
config XIP_ROM_SIZE
|
||||
hex
|
||||
default 0x80000
|
||||
depends on CPU_AMD_AGESA_FAMILY14
|
||||
|
||||
config HAVE_INIT_TIMER
|
||||
bool
|
||||
default y
|
||||
depends on CPU_AMD_AGESA_FAMILY14
|
||||
|
||||
config HIGH_SCRATCH_MEMORY_SIZE
|
||||
hex
|
||||
# Assume the maximum size of stack as (0xA0000 - 0x30000 + 0x1000)
|
||||
default 0x71000
|
||||
depends on CPU_AMD_AGESA_FAMILY14
|
||||
|
||||
endif
|
||||
|
|
|
@ -22,12 +22,11 @@ config CPU_AMD_AGESA_FAMILY15
|
|||
select PCI_IO_CFG_EXT
|
||||
select X86_AMD_FIXED_MTRRS
|
||||
|
||||
if CPU_AMD_AGESA_FAMILY15
|
||||
|
||||
config CPU_ADDR_BITS
|
||||
int
|
||||
default 48
|
||||
depends on CPU_AMD_AGESA_FAMILY15
|
||||
|
||||
if CPU_AMD_AGESA_FAMILY15
|
||||
|
||||
config CPU_AMD_SOCKET_G34
|
||||
bool
|
||||
|
|
|
@ -22,59 +22,48 @@ config CPU_AMD_AGESA_FAMILY15_TN
|
|||
select PCI_IO_CFG_EXT
|
||||
select X86_AMD_FIXED_MTRRS
|
||||
|
||||
if CPU_AMD_AGESA_FAMILY15_TN
|
||||
|
||||
config CPU_ADDR_BITS
|
||||
int
|
||||
default 48
|
||||
depends on CPU_AMD_AGESA_FAMILY15_TN
|
||||
|
||||
config CPU_SOCKET_TYPE
|
||||
hex
|
||||
default 0x10
|
||||
depends on CPU_AMD_AGESA_FAMILY15_TN
|
||||
|
||||
# DDR2 and REG
|
||||
config DIMM_SUPPORT
|
||||
hex
|
||||
default 0x0104
|
||||
depends on CPU_AMD_AGESA_FAMILY15_TN
|
||||
|
||||
config EXT_RT_TBL_SUPPORT
|
||||
bool
|
||||
default n
|
||||
depends on CPU_AMD_AGESA_FAMILY15_TN
|
||||
|
||||
config EXT_CONF_SUPPORT
|
||||
bool
|
||||
default n
|
||||
depends on CPU_AMD_AGESA_FAMILY15_TN
|
||||
|
||||
config CBB
|
||||
hex
|
||||
default 0x0
|
||||
depends on CPU_AMD_AGESA_FAMILY15_TN
|
||||
|
||||
config CDB
|
||||
hex
|
||||
default 0x18
|
||||
depends on CPU_AMD_AGESA_FAMILY15_TN
|
||||
|
||||
config XIP_ROM_BASE
|
||||
hex
|
||||
default 0xfff80000
|
||||
depends on CPU_AMD_AGESA_FAMILY15_TN
|
||||
|
||||
config XIP_ROM_SIZE
|
||||
hex
|
||||
default 0x100000
|
||||
depends on CPU_AMD_AGESA_FAMILY15_TN
|
||||
|
||||
config HAVE_INIT_TIMER
|
||||
bool
|
||||
default y
|
||||
depends on CPU_AMD_AGESA_FAMILY15_TN
|
||||
|
||||
config HIGH_SCRATCH_MEMORY_SIZE
|
||||
hex
|
||||
# Assume the maximum size of stack as (0xA0000 - 0x30000 + 0x1000)
|
||||
default 0xA1000
|
||||
depends on CPU_AMD_AGESA_FAMILY15_TN
|
||||
|
||||
endif
|
||||
|
|
|
@ -7,6 +7,7 @@ config CPU_AMD_MODEL_10XXX
|
|||
select UDELAY_LAPIC
|
||||
|
||||
if CPU_AMD_MODEL_10XXX
|
||||
|
||||
config CPU_ADDR_BITS
|
||||
int
|
||||
default 48
|
||||
|
|
|
@ -6,32 +6,30 @@ config CPU_AMD_SOCKET_AM2R2
|
|||
select CACHE_AS_RAM
|
||||
select X86_AMD_FIXED_MTRRS
|
||||
|
||||
if CPU_AMD_SOCKET_AM2R2
|
||||
|
||||
config CPU_SOCKET_TYPE
|
||||
hex
|
||||
default 0x11
|
||||
depends on CPU_AMD_SOCKET_AM2R2
|
||||
|
||||
config EXT_RT_TBL_SUPPORT
|
||||
bool
|
||||
default n
|
||||
depends on CPU_AMD_SOCKET_AM2R2
|
||||
|
||||
config EXT_CONF_SUPPORT
|
||||
bool
|
||||
default n
|
||||
depends on CPU_AMD_SOCKET_AM2R2
|
||||
|
||||
config CBB
|
||||
hex
|
||||
default 0x0
|
||||
depends on CPU_AMD_SOCKET_AM2R2
|
||||
|
||||
config CDB
|
||||
hex
|
||||
default 0x18
|
||||
depends on CPU_AMD_SOCKET_AM2R2
|
||||
|
||||
config XIP_ROM_SIZE
|
||||
hex
|
||||
default 0x80000
|
||||
depends on CPU_AMD_SOCKET_AM2R2
|
||||
|
||||
endif
|
||||
|
|
|
@ -6,33 +6,30 @@ config CPU_AMD_SOCKET_AM3
|
|||
select CACHE_AS_RAM
|
||||
select X86_AMD_FIXED_MTRRS
|
||||
|
||||
if CPU_AMD_SOCKET_AM3
|
||||
|
||||
config CPU_SOCKET_TYPE
|
||||
hex
|
||||
default 0x11
|
||||
depends on CPU_AMD_SOCKET_AM3
|
||||
|
||||
config EXT_RT_TBL_SUPPORT
|
||||
bool
|
||||
default n
|
||||
depends on CPU_AMD_SOCKET_AM3
|
||||
|
||||
config EXT_CONF_SUPPORT
|
||||
bool
|
||||
default n
|
||||
depends on CPU_AMD_SOCKET_AM3
|
||||
|
||||
config CBB
|
||||
hex
|
||||
default 0x0
|
||||
depends on CPU_AMD_SOCKET_AM3
|
||||
|
||||
config CDB
|
||||
hex
|
||||
default 0x18
|
||||
depends on CPU_AMD_SOCKET_AM3
|
||||
|
||||
config XIP_ROM_SIZE
|
||||
hex
|
||||
default 0x80000
|
||||
depends on CPU_AMD_SOCKET_AM3
|
||||
|
||||
endif
|
||||
|
|
|
@ -6,32 +6,30 @@ config CPU_AMD_SOCKET_ASB2
|
|||
select CACHE_AS_RAM
|
||||
select X86_AMD_FIXED_MTRRS
|
||||
|
||||
if CPU_AMD_SOCKET_ASB2
|
||||
|
||||
config CPU_SOCKET_TYPE
|
||||
hex
|
||||
default 0x13
|
||||
depends on CPU_AMD_SOCKET_ASB2
|
||||
|
||||
config EXT_RT_TBL_SUPPORT
|
||||
bool
|
||||
default n
|
||||
depends on CPU_AMD_SOCKET_ASB2
|
||||
|
||||
config EXT_CONF_SUPPORT
|
||||
bool
|
||||
default n
|
||||
depends on CPU_AMD_SOCKET_ASB2
|
||||
|
||||
config CBB
|
||||
hex
|
||||
default 0x0
|
||||
depends on CPU_AMD_SOCKET_ASB2
|
||||
|
||||
config CDB
|
||||
hex
|
||||
default 0x18
|
||||
depends on CPU_AMD_SOCKET_ASB2
|
||||
|
||||
config XIP_ROM_SIZE
|
||||
hex
|
||||
default 0x80000
|
||||
depends on CPU_AMD_SOCKET_ASB2
|
||||
|
||||
endif
|
||||
|
|
|
@ -6,33 +6,30 @@ config CPU_AMD_SOCKET_C32_NON_AGESA
|
|||
select CACHE_AS_RAM
|
||||
select X86_AMD_FIXED_MTRRS
|
||||
|
||||
if CPU_AMD_SOCKET_C32_NON_AGESA
|
||||
|
||||
config CPU_SOCKET_TYPE
|
||||
hex
|
||||
default 0x14
|
||||
depends on CPU_AMD_SOCKET_C32_NON_AGESA
|
||||
|
||||
config EXT_RT_TBL_SUPPORT
|
||||
bool
|
||||
default n
|
||||
depends on CPU_AMD_SOCKET_C32_NON_AGESA
|
||||
|
||||
config EXT_CONF_SUPPORT
|
||||
bool
|
||||
default n
|
||||
depends on CPU_AMD_SOCKET_C32_NON_AGESA
|
||||
|
||||
config CBB
|
||||
hex
|
||||
default 0x0
|
||||
depends on CPU_AMD_SOCKET_C32_NON_AGESA
|
||||
|
||||
config CDB
|
||||
hex
|
||||
default 0x18
|
||||
depends on CPU_AMD_SOCKET_C32_NON_AGESA
|
||||
|
||||
config XIP_ROM_SIZE
|
||||
hex
|
||||
default 0x80000
|
||||
depends on CPU_AMD_SOCKET_C32_NON_AGESA
|
||||
|
||||
endif
|
||||
|
|
|
@ -5,32 +5,30 @@ config CPU_AMD_SOCKET_F_1207
|
|||
select CACHE_AS_RAM
|
||||
select X86_AMD_FIXED_MTRRS
|
||||
|
||||
if CPU_AMD_SOCKET_F_1207
|
||||
|
||||
config CPU_SOCKET_TYPE
|
||||
hex
|
||||
default 0x10
|
||||
depends on CPU_AMD_SOCKET_F_1207
|
||||
|
||||
config EXT_RT_TBL_SUPPORT
|
||||
bool
|
||||
default n
|
||||
depends on CPU_AMD_SOCKET_F_1207
|
||||
|
||||
config EXT_CONF_SUPPORT
|
||||
bool
|
||||
default n
|
||||
depends on CPU_AMD_SOCKET_F_1207
|
||||
|
||||
config CBB
|
||||
hex
|
||||
default 0x0
|
||||
depends on CPU_AMD_SOCKET_F_1207
|
||||
|
||||
config CDB
|
||||
hex
|
||||
default 0x18
|
||||
depends on CPU_AMD_SOCKET_F_1207
|
||||
|
||||
config XIP_ROM_SIZE
|
||||
hex
|
||||
default 0x80000
|
||||
depends on CPU_AMD_SOCKET_F_1207
|
||||
|
||||
endif
|
||||
|
|
Loading…
Reference in New Issue