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Revert "nb/amd/mct_ddr3: Disable MCE framework during DRAM training" 

After substantial testing it has been determined that it is neither
required nor safe to disable the DRAM MCA during initial startup.

This (mostly) reverts commit c094d99611.
The minor debugging enhancements from that commit were left in place.
Tested-On: ASUS KGPE-D16
Config-CPU: 1x Opteron 6262HE
Config-RAM: 4x Crucial 36KSF1G72PZ-1G6M1
Config-RAM: 1x Kingston 9965516-483.A00LF
Change-Id: I58fcc296b8c45ecaedf540951c365e4ce52baaf5
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/14446
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Timothy Pearson 2016-04-21 01:18:36 -05:00 committed by Martin Roth
parent 5a359365b9
commit 8b9c807d72
3 changed files with 27 additions and 27 deletions
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13
src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
View File

@ -8049,19 +8049,6 @@ void mct_SetDramConfigHi_D(struct MCTStatStruc *pMCTstat,
printk(BIOS_DEBUG, "mct_SetDramConfigHi_D: DramConfigHi: %08x\n", DramConfigHi);
/* Prevent lockups on parity errors during initial DCT startup */
if (!pDCTstat->mca_config_backed_up) {
dword = Get_NB32(pDCTstat->dev_nbmisc, 0x44);
pDCTstat->sync_flood_on_dram_err = (dword >> 30) & 0x1;
pDCTstat->sync_flood_on_any_uc_err = (dword >> 21) & 0x1;
pDCTstat->sync_flood_on_uc_dram_ecc_err = (dword >> 2) & 0x1;
dword &= ~(0x1 << 30);
dword &= ~(0x1 << 21);
dword &= ~(0x1 << 2);
Set_NB32(pDCTstat->dev_nbmisc, 0x44, dword);
pDCTstat->mca_config_backed_up = 1;
}
/* Program the DRAM Configuration High register */
Set_NB32_DCT(dev, dct, 0x94, DramConfigHi);

6
src/northbridge/amd/amdmct/mct_ddr3/mct_d.h
View File

@ -581,12 +581,6 @@ struct DCTStatStruc { /* A per Node structure*/
uint8_t NbPstateThreshold;
uint8_t NbPstateHi;
/* MCA backup variables */
uint8_t mca_config_backed_up;
uint8_t sync_flood_on_dram_err;
uint8_t sync_flood_on_any_uc_err;
uint8_t sync_flood_on_uc_dram_ecc_err;
/* New for LB Support */
u8 NodePresent;
u32 dev_host;

35
src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c
View File

@ -84,6 +84,10 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA)
u32 val;
u16 nvbits;
uint32_t dword;
uint8_t sync_flood_on_dram_err[MAX_NODES_SUPPORTED];
uint8_t sync_flood_on_any_uc_err[MAX_NODES_SUPPORTED];
mctHookBeforeECC();
/* Construct these booleans, based on setup options, for easy handling
@ -116,6 +120,24 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA)
pDCTstat = pDCTstatA + Node;
if (NodePresent_D(Node)) {
dword = Get_NB32(pDCTstat->dev_nbmisc, 0x44);
sync_flood_on_dram_err[Node] = (dword >> 30) & 0x1;
sync_flood_on_any_uc_err[Node] = (dword >> 21) & 0x1;
dword &= ~(0x1 << 30);
dword &= ~(0x1 << 21);
Set_NB32(pDCTstat->dev_nbmisc, 0x44, dword);
uint32_t mc4_status_high = pci_read_config32(pDCTstat->dev_nbmisc, 0x4c);
uint32_t mc4_status_low = pci_read_config32(pDCTstat->dev_nbmisc, 0x48);
if ((mc4_status_high & (0x1 << 31)) && (mc4_status_high != 0xffffffff)) {
printk(BIOS_WARNING, "WARNING: MC4 Machine Check Exception detected!\n"
"Signature: %08x%08x\n", mc4_status_high, mc4_status_low);
}
/* Clear MC4 error status */
pci_write_config32(pDCTstat->dev_nbmisc, 0x48, 0x0);
pci_write_config32(pDCTstat->dev_nbmisc, 0x4c, 0x0);
/* Clear the RAM before enabling ECC to prevent MCE-related lockups */
DCTMemClr_Init_D(pMCTstat, pDCTstat);
DCTMemClr_Sync_D(pMCTstat, pDCTstat);
@ -265,14 +287,11 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA)
pci_write_config32(pDCTstat->dev_nbmisc, 0x48, 0x0);
pci_write_config32(pDCTstat->dev_nbmisc, 0x4c, 0x0);
/* Restore MCA settings */
if (pDCTstat->mca_config_backed_up) {
val = pci_read_config32(pDCTstat->dev_nbmisc, 0x44);
val |= (pDCTstat->sync_flood_on_dram_err & 0x1) << 30;
val |= (pDCTstat->sync_flood_on_any_uc_err & 0x1) << 21;
val |= (pDCTstat->sync_flood_on_uc_dram_ecc_err & 0x1) << 2;
pci_write_config32(pDCTstat->dev_nbmisc, 0x44, val);
}
/* Restore previous MCA error handling settings */
dword = Get_NB32(pDCTstat->dev_nbmisc, 0x44);
dword |= (sync_flood_on_dram_err[Node] & 0x1) << 30;
dword |= (sync_flood_on_any_uc_err[Node] & 0x1) << 21;
Set_NB32(pDCTstat->dev_nbmisc, 0x44, dword);
}
}
}