gm45/gma.c: clean up some registers
According to "G45: Volume 3: Display Register Intel ® 965G Express Chipset Family and Intel ® G35 Express Chipset Graphics Controller" some registries are set incorrectly in gm45/gma.c. Some values are changed after comparing them with the values the i915 linux kernel (3.13 was used) module sets while modesetting. The values were obtained using 'intel_reg' from intel-gpu-tools, during a normal boot and with 'nomodeset' as a kernel argument. Some registers that don't exist on gm45 are set in gma.c, which is probably the result of copying code from a more recent intel northbridge. The result is that that gm45 laptops with wxga displays still work as before. gm45 laptops with wxga+ or higher resolution now just work, where previously a black screen was shown. TEST: build with native graphic init and flash on a gm45 target, like lenovo x200. Change-Id: If66b60c7189997c558270f9e474851fe7e2219f1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/16217 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Arthur Heymans
Martin Roth
parent
e52592078e
commit
8ba2010d12
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@ -47,60 +47,6 @@ void gtt_write(u32 reg, u32 data)
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write32(res2mmio(gtt_res, reg, 0), data);
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}
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static void power_port(u8 *mmio)
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{
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read32(mmio + 0x00061100); // = 0x00000000
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write32(mmio + 0x00061100, 0x00000000);
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write32(mmio + 0x00061100, 0x00010000);
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read32(mmio + 0x00061100); // = 0x00010000
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read32(mmio + 0x00061100); // = 0x00010000
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read32(mmio + 0x00061100); // = 0x00000000
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write32(mmio + 0x00061100, 0x00000000);
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read32(mmio + 0x00061100); // = 0x00000000
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read32(mmio + 0x00064200); // = 0x0000001c
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write32(mmio + 0x00064210, 0x8004003e);
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write32(mmio + 0x00064214, 0x80060002);
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write32(mmio + 0x00064218, 0x01000000);
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read32(mmio + 0x00064210); // = 0x5144003e
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write32(mmio + 0x00064210, 0x5344003e);
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read32(mmio + 0x00064210); // = 0x0144003e
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write32(mmio + 0x00064210, 0x8074003e);
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read32(mmio + 0x00064210); // = 0x5144003e
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read32(mmio + 0x00064210); // = 0x5144003e
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write32(mmio + 0x00064210, 0x5344003e);
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read32(mmio + 0x00064210); // = 0x0144003e
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write32(mmio + 0x00064210, 0x8074003e);
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read32(mmio + 0x00064210); // = 0x5144003e
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read32(mmio + 0x00064210); // = 0x5144003e
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write32(mmio + 0x00064210, 0x5344003e);
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read32(mmio + 0x00064210); // = 0x0144003e
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write32(mmio + 0x00064210, 0x8074003e);
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read32(mmio + 0x00064210); // = 0x5144003e
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read32(mmio + 0x00064210); // = 0x5144003e
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write32(mmio + 0x00064210, 0x5344003e);
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write32(mmio + 0x00064f00, 0x0100030c);
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write32(mmio + 0x00064f04, 0x00b8230c);
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write32(mmio + 0x00064f08, 0x06f8930c);
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write32(mmio + 0x00064f0c, 0x09f8e38e);
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write32(mmio + 0x00064f10, 0x00b8030c);
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write32(mmio + 0x00064f14, 0x0b78830c);
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write32(mmio + 0x00064f18, 0x0ff8d3cf);
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write32(mmio + 0x00064f1c, 0x01e8030c);
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write32(mmio + 0x00064f20, 0x0ff863cf);
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write32(mmio + 0x00064f24, 0x0ff803cf);
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write32(mmio + 0x000c4030, 0x00001000);
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read32(mmio + 0x00044000); // = 0x00000000
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write32(mmio + 0x00044030, 0x00001000);
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read32(mmio + 0x00061150); // = 0x0000001c
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write32(mmio + 0x00061150, 0x0000089c);
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write32(mmio + 0x000fcc00, 0x01986f00);
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write32(mmio + 0x000fcc0c, 0x01986f00);
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write32(mmio + 0x000fcc18, 0x01986f00);
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write32(mmio + 0x000fcc24, 0x01986f00);
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read32(mmio + 0x00044000); // = 0x00000000
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read32(mmio + LVDS); // = 0x40000002
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}
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static void intel_gma_init(const struct northbridge_intel_gm45_config *info,
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u8 *mmio, u32 physbase, u16 piobase, u32 lfb)
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{
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@ -150,8 +96,6 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info,
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for (i = 0; i <= 0x18; i++)
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vga_cr_write(i, cr[i]);
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power_port(mmio);
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intel_gmbus_read_edid(mmio + GMBUS0, 3, 0x50, edid_data, 128);
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decode_edid(edid_data,
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sizeof(edid_data), &edid);
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@ -277,28 +221,32 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info,
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(hpolarity << 20) | (vpolarity << 21)
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| (mode->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
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| LVDS_CLOCK_BOTH_POWERUP_ALL : 0)
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| LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL);
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| LVDS_ENABLE_DITHER
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| LVDS_CLOCK_A_POWERUP_ALL
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| LVDS_PIPE(0));
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mdelay(1);
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write32(mmio + PP_CONTROL, PANEL_UNLOCK_REGS
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| (read32(mmio + PP_CONTROL) & ~PANEL_UNLOCK_MASK));
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write32(mmio + FP0(0),
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((pixel_n - 2) << 16)
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| ((pixel_m1 - 2) << 8) | pixel_m2);
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| ((pixel_m1 - 2) << 8) | (pixel_m2 - 2));
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write32(mmio + DPLL(0),
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DPLL_VCO_ENABLE | DPLLB_MODE_LVDS
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| DPLL_VGA_MODE_DIS
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| (mode->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7
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: DPLLB_LVDS_P2_CLOCK_DIV_14)
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| (0x10000 << (pixel_p1 - 1))
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| ((info->gfx.use_spread_spectrum_clock ? 3 : 0) << 13)
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| (0x1 << (pixel_p1 - 1)));
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| (6 << PLL_LOAD_PULSE_PHASE_SHIFT));
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mdelay(1);
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write32(mmio + DPLL(0),
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DPLL_VCO_ENABLE | DPLLB_MODE_LVDS
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| DPLL_VGA_MODE_DIS
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| (mode->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7
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: DPLLB_LVDS_P2_CLOCK_DIV_14)
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| (0x10000 << (pixel_p1 - 1))
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| ((info->gfx.use_spread_spectrum_clock ? 3 : 0) << 13)
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| (0x1 << (pixel_p1 - 1)));
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| (6 << PLL_LOAD_PULSE_PHASE_SHIFT));
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/* Re-lock the registers. */
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write32(mmio + PP_CONTROL,
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(read32(mmio + PP_CONTROL) & ~PANEL_UNLOCK_MASK));
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@ -307,7 +255,9 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info,
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(hpolarity << 20) | (vpolarity << 21)
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| (mode->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
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| LVDS_CLOCK_BOTH_POWERUP_ALL : 0)
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| LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL);
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| LVDS_CLOCK_A_POWERUP_ALL
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| LVDS_ENABLE_DITHER
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| LVDS_PIPE(0));
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write32(mmio + HTOTAL(0),
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((hactive + right_border + hblank - 1) << 16)
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@ -324,7 +274,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info,
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write32(mmio + VBLANK(0), ((vactive + bottom_border + vblank - 1) << 16)
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| (vactive + bottom_border - 1));
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write32(mmio + VSYNC(0),
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(vactive + bottom_border + vfront_porch + vsync - 1)
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((vactive + bottom_border + vfront_porch + vsync - 1) << 16)
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| (vactive + bottom_border + vfront_porch - 1));
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write32(mmio + PIPECONF(0), PIPECONF_DISABLE);
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@ -335,7 +285,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info,
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| (vactive - 1));
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write32(mmio + PF_CTL(0), 0);
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write32(mmio + PF_WIN_SZ(0), 0);
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write32(mmio + PFIT_CONTROL, 0x20000000);
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write32(mmio + PFIT_CONTROL, 0);
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} else {
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write32(mmio + PIPESRC(0), (639 << 16) | 399);
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write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3);
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@ -362,7 +312,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info,
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write32(mmio + PIPECONF(0), PIPECONF_ENABLE | PIPECONF_BPP_6 | PIPECONF_DITHER_EN);
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if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
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write32(mmio + VGACNTRL, 0xc4008e | VGA_DISP_DISABLE);
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write32(mmio + VGACNTRL, VGA_DISP_DISABLE);
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write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE
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| DISPPLANE_BGRX888);
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mdelay(1);
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@ -370,37 +320,13 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info,
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write32(mmio + VGACNTRL, 0xc4008e);
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}
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write32(mmio + TRANS_HTOTAL(0),
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((hactive + right_border + hblank - 1) << 16)
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| (hactive - 1));
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write32(mmio + TRANS_HBLANK(0),
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((hactive + right_border + hblank - 1) << 16)
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| (hactive + right_border - 1));
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write32(mmio + TRANS_HSYNC(0),
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((hactive + right_border + hfront_porch + hsync - 1) << 16)
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| (hactive + right_border + hfront_porch - 1));
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write32(mmio + TRANS_VTOTAL(0),
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((vactive + bottom_border + vblank - 1) << 16)
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| (vactive - 1));
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write32(mmio + TRANS_VBLANK(0),
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((vactive + bottom_border + vblank - 1) << 16)
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| (vactive + bottom_border - 1));
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write32(mmio + TRANS_VSYNC(0),
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(vactive + bottom_border + vfront_porch + vsync - 1)
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| (vactive + bottom_border + vfront_porch - 1));
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write32(mmio + 0x00060100, 0xb01c4000);
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write32(mmio + 0x000f000c, 0xb01a2050);
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mdelay(1);
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write32(mmio + TRANSCONF(0), TRANS_ENABLE | TRANS_6BPC
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);
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write32(mmio + LVDS,
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LVDS_PORT_ENABLE
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write32(mmio + LVDS, LVDS_PORT_ENABLE
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| (hpolarity << 20) | (vpolarity << 21)
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| (mode->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
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| LVDS_CLOCK_BOTH_POWERUP_ALL : 0)
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| LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL);
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| LVDS_CLOCK_A_POWERUP_ALL
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| LVDS_ENABLE_DITHER
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| LVDS_PIPE(0));
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write32(mmio + PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET);
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