google/puff: Enable ASPM of RTL8111H

With kernel 5.15, puff hangs during power idle tests because
the NIC does not enter ASPM L1.2. We add "enable_aspm_l1_2" in
devicetree for RTL8111H to enable ASPM L1.2.

BUG=b:268859220, b:279618219
TEST=emerge and run power.Idle

Change-Id: I129dfd79e8112191453be513b2e3a260429b3030
Signed-off-by: Alexis Savery <asavery@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77570
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/google/puff/variants/ambassador/overridetree.cb

@@ -395,6 +395,7 @@ chip soc/intel/cannonlake
 				register "customized_leds" = "0x05af"
 				register "wake" = "GPE0_DW1_07" # GPP_C7
 				register "device_index" = "0"
+				register "enable_aspm_l1_2" = "1"
 				device pci 00.0 on end
 			end
 			register "PcieRpSlotImplemented[6]" = "1"

src/mainboard/google/puff/variants/duffy/overridetree.cb

@@ -454,6 +454,7 @@ chip soc/intel/cannonlake
 				register "customized_leds" = "0x05af"
 				register "wake" = "GPE0_DW1_07" # GPP_C7
 				register "device_index" = "0"
+				register "enable_aspm_l1_2" = "1"
 				device pci 00.0 on end
 			end
 			register "PcieRpSlotImplemented[6]" = "1"

src/mainboard/google/puff/variants/faffy/overridetree.cb

@@ -428,6 +428,7 @@ chip soc/intel/cannonlake
 				register "customized_leds" = "0x05af"
 				register "wake" = "GPE0_DW1_07" # GPP_C7
 				register "device_index" = "0"
+				register "enable_aspm_l1_2" = "1"
 				device pci 00.0 on end
 			end
 			register "PcieRpSlotImplemented[6]" = "1"

src/mainboard/google/puff/variants/genesis/overridetree.cb

@@ -425,6 +425,7 @@ chip soc/intel/cannonlake
 				register "customized_leds" = "0x05af"
 				register "wake" = "GPE0_DW1_07" # GPP_C7
 				register "device_index" = "0"
+				register "enable_aspm_l1_2" = "1"
 				device pci 00.0 on end
 			end
 		end

src/mainboard/google/puff/variants/kaisa/overridetree.cb

@@ -454,6 +454,7 @@ chip soc/intel/cannonlake
 				register "customized_leds" = "0x05af"
 				register "wake" = "GPE0_DW1_07" # GPP_C7
 				register "device_index" = "0"
+				register "enable_aspm_l1_2" = "1"
 				device pci 00.0 on end
 			end
 			register "PcieRpSlotImplemented[6]" = "1"

src/mainboard/google/puff/variants/moonbuggy/overridetree.cb

@@ -427,6 +427,7 @@ chip soc/intel/cannonlake
 				register "customized_leds" = "0x05af"
 				register "wake" = "GPE0_DW1_07" # GPP_C7
 				register "device_index" = "0"
+				register "enable_aspm_l1_2" = "1"
 				device pci 00.0 on end
 			end
 		end

src/mainboard/google/puff/variants/noibat/overridetree.cb

@@ -365,6 +365,7 @@ chip soc/intel/cannonlake
 				register "customized_leds" = "0x05af"
 				register "wake" = "GPE0_DW1_07" # GPP_C7
 				register "device_index" = "0"
+				register "enable_aspm_l1_2" = "1"
 				device pci 00.0 on end
 			end
 			register "PcieRpSlotImplemented[6]" = "1"

src/mainboard/google/puff/variants/puff/overridetree.cb

@@ -389,6 +389,7 @@ chip soc/intel/cannonlake
 				register "customized_leds" = "0x05af"
 				register "wake" = "GPE0_DW1_07" # GPP_C7
 				register "device_index" = "0"
+				register "enable_aspm_l1_2" = "1"
 				device pci 00.0 on end
 			end
 			register "PcieRpSlotImplemented[6]" = "1"

src/mainboard/google/puff/variants/scout/overridetree.cb

@@ -405,6 +405,7 @@ chip soc/intel/cannonlake
 				register "customized_leds" = "0x05af"
 				register "wake" = "GPE0_DW1_07" # GPP_C7
 				register "device_index" = "0"
+				register "enable_aspm_l1_2" = "1"
 				device pci 00.0 on end
 			end
 		end

src/mainboard/google/puff/variants/wyvern/overridetree.cb

@@ -390,6 +390,7 @@ chip soc/intel/cannonlake
 				register "customized_leds" = "0x05af"
 				register "wake" = "GPE0_DW1_07" # GPP_C7
 				register "device_index" = "0"
+				register "enable_aspm_l1_2" = "1"
 				device pci 00.0 on end
 			end
 			register "PcieRpSlotImplemented[6]" = "1"