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soc/intel/apl/graphics: add missing left-shift 

According to doc# IHD-OS-BXT-Vol 2b-05.17 the cycle delay is in the bit
range 8:4 of register PP_CONTROL. The current code writes the value to
bits 4:0, though. Correct that by shifting the value left by 4 bits.

Change-Id: If407932c847da39b19e307368c9e52ba1c93bccd
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Michael Niewöhner 2020-12-19 22:22:32 +01:00 committed by Nico Huber
parent e653942453
commit 8ba96b91dc
1 changed files with 2 additions and 1 deletions
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3
src/soc/intel/apollolake/graphics.c
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@ -17,7 +17,8 @@ static void graphics_configure_panelpower(
const unsigned int offset = panel_idx * 0x100; const unsigned int offset = panel_idx * 0x100;
uint32_t reg32; uint32_t reg32;
reg32 = ((DIV_ROUND_UP(pp->cycle_delay_ms, 100) + 1) & 0x1f) | PANEL_POWER_RESET; reg32 = (DIV_ROUND_UP(pp->cycle_delay_ms, 100) + 1) << 4 & 0x1f0;
reg32 |= PANEL_POWER_RESET;
write32(mmio + PCH_PP_CONTROL + offset, reg32); write32(mmio + PCH_PP_CONTROL + offset, reg32);
reg32 = pp->up_delay_ms * 10 << 16; reg32 = pp->up_delay_ms * 10 << 16;