From 8bd8cd3a222bb8d54fd2510728c87dc6909b287c Mon Sep 17 00:00:00 2001
From: Shelley Chen <shchen@chromium.org>
Date: Mon, 22 Jan 2018 10:26:31 -0800
Subject: [PATCH] mainboard/google/fizz: Tune audio i2c parameters

Tune I2C params for I2C bus 5 to ensure that the frequency does not
exceed 400KHz.

BUG=b:65058277
BRANCH=None
TEST=Measured bus frequency for audio <= 400MHz

Change-Id: I18bca023a6a0fe21e6f46f8688264d3c04d77f25
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/23359
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
---
 src/mainboard/google/fizz/devicetree.cb | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/src/mainboard/google/fizz/devicetree.cb b/src/mainboard/google/fizz/devicetree.cb
index 81b5dc5603..8cf4e52fb9 100644
--- a/src/mainboard/google/fizz/devicetree.cb
+++ b/src/mainboard/google/fizz/devicetree.cb
@@ -247,6 +247,17 @@ chip soc/intel/skylake
 		 .early_init = 1,
 	}"
 
+	# audio
+	register "i2c[5]" = "{
+		 .speed = I2C_SPEED_FAST,
+		 .speed_config[0] = {
+			.speed = I2C_SPEED_FAST,
+			.scl_lcnt = 194,
+			.scl_hcnt = 100,
+			.sda_hold = 36,
+		},
+	}"
+
 	# Must leave UART0 enabled or SD/eMMC will not work as PCI
 	register "SerialIoDevMode" = "{
 		[PchSerialIoIndexI2C0]  = PchSerialIoDisabled,