Various Super I/O fixes and corrections.
- VIA VT1211: - Add missing LDNs and respective code to handle them. - Add some TODOs for other stuff that needs fixing. - Use VT1211_SP1 instead of hardcoding the LDN number (2). - Fixup pnp_dev_info[] as per datasheet, but some TODOs remain. - Various coding style fixes and changes to u8/u16/etc. - Serverengines Pilot: Various coding style fixes and changes to u8/u16/etc. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6030 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Uwe Hermann
parent
9915944b18
commit
8c02368e2d
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@ -44,15 +44,14 @@ static void m3885x_init(device_t dev)
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m3885_configure_multikey();
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}
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static void m3885x_read_resources(device_t dev)
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{
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// nothing, but this function avoids an error on serial console.
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/* Nothing, but this function avoids an error on serial console. */
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}
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static void m3885x_enable_resources(device_t dev)
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{
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// nothing, but this function avoids an error on serial console.
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/* Nothing, but this function avoids an error on serial console. */
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}
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static struct device_operations ops = {
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@ -74,5 +73,3 @@ struct chip_operations superio_renesas_m3885x_ops = {
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CHIP_NAME("Renesas M3885x Super I/O")
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.enable_dev = enable_dev,
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};
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@ -21,8 +21,8 @@
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/* PILOT Super I/O is only based on LPC observation done on factory system. */
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#define PILOT_SP1 0x02 /* Com1 */
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#define PILOT_LD1 0x01 /* Logical device 1 */
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#define PILOT_SP1 0x02 /* Com1 */
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#define PILOT_LD4 0x04 /* Logical device 4 */
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#define PILOT_LD5 0x05 /* Logical device 5 */
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#define PILOT_LD7 0x07 /* Logical device 7 */
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@ -29,7 +29,7 @@
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*/
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static void pilot_early_init(device_t dev)
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{
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unsigned port = dev >> 8;
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u16 port = dev >> 8;
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print_debug("Using port: ");
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print_debug_hex16(port);
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@ -55,6 +55,7 @@ static void pilot_early_init(device_t dev)
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pnp_set_enable(PNP_DEV(port, 0x3), 0);
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pnp_exit_ext_func_mode(dev);
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*/
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pnp_enter_ext_func_mode(dev);
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pnp_set_logical_device(PNP_DEV(port, 0x4));
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pnp_exit_ext_func_mode(dev);
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@ -95,6 +96,7 @@ static void pilot_early_init(device_t dev)
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pnp_enter_ext_func_mode(dev);
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pnp_set_enable(PNP_DEV(port, 0x7), 0);
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pnp_exit_ext_func_mode(dev);
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/*
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pnp_enter_ext_func_mode(dev);
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pnp_set_logical_device(PNP_DEV(port, 0x8));
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@ -25,20 +25,20 @@
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#include "pilot.h"
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/* Pilot uses 0x5A/0xA5 pattern to actiavte deactivate config access. */
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static inline void pnp_enter_ext_func_mode(device_t dev)
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static void pnp_enter_ext_func_mode(device_t dev)
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{
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unsigned port = dev >> 8;
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u16 port = dev >> 8;
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outb(0x5A, port);
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}
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static void pnp_exit_ext_func_mode(device_t dev)
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{
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unsigned port = dev >> 8;
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u16 port = dev >> 8;
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outb(0xA5, port);
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}
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/* Serial config is a fairly standard procedure. */
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static void pilot_enable_serial(device_t dev, unsigned iobase)
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static void pilot_enable_serial(device_t dev, u16 iobase)
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{
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pnp_enter_ext_func_mode(dev);
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pnp_set_logical_device(dev);
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@ -51,7 +51,7 @@ static void pilot_disable_serial(device_t dev)
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{
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pnp_enter_ext_func_mode(dev);
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pnp_set_logical_device(dev);
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pnp_set_iobase(dev, PNP_IDX_IO0, 0x00);
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pnp_set_iobase(dev, PNP_IDX_IO0, 0x0000);
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pnp_set_enable(dev, 0);
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pnp_exit_ext_func_mode(dev);
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}
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@ -18,5 +18,5 @@
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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#config chip.h
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ramstage-$(CONFIG_SUPERIO_VIA_VT1211) += vt1211.c
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@ -18,8 +18,8 @@
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef _SUPERIO_VIA_VT1211
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#define _SUPERIO_VIA_VT1211
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#ifndef SUPERIO_VIA_VT1211_CHIP_H
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#define SUPERIO_VIA_VT1211_CHIP_H
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#include <uart8250.h>
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@ -29,4 +29,4 @@ struct superio_via_vt1211_config {
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struct uart8250 com1, com2;
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};
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#endif /* _SUPERIO_VIA_VT1211 */
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#endif
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@ -19,33 +19,30 @@
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* MA 02110-1301 USA
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*/
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/* vt1211 routines and defines*/
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#include <arch/io.h>
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pnp.h>
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#include <uart8250.h>
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#include <stdlib.h>
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#include "vt1211.h"
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#include "chip.h"
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static unsigned char vt1211hwmonitorinits[]={
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0x10,0x3, 0x11,0x10, 0x12,0xd, 0x13,0x7f,
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static u8 hwm_io_regs[] = {
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0x10,0x03, 0x11,0x10, 0x12,0x0d, 0x13,0x7f,
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0x14,0x21, 0x15,0x81, 0x16,0xbd, 0x17,0x8a,
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0x18,0x0, 0x19,0x0, 0x1a,0x0, 0x1b,0x0,
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0x1d,0xff, 0x1e,0x0, 0x1f,0x73, 0x20,0x67,
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0x18,0x00, 0x19,0x00, 0x1a,0x00, 0x1b,0x00,
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0x1d,0xff, 0x1e,0x00, 0x1f,0x73, 0x20,0x67,
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0x21,0xc1, 0x22,0xca, 0x23,0x74, 0x24,0xc2,
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0x25,0xc7, 0x26,0xc9, 0x27,0x7f, 0x29,0x0,
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0x2a,0x0, 0x2b,0xff, 0x2c,0x0, 0x2d,0xff,
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0x2e,0x0, 0x2f,0xff, 0x30,0x0, 0x31,0xff,
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0x32,0x0, 0x33,0xff, 0x34,0x0, 0x39,0xff,
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0x3a,0x0, 0x3b,0xff, 0x3c,0xff, 0x3d,0xff,
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0x3e,0x0, 0x3f,0xb0, 0x43,0xff, 0x44,0xff,
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0x46,0xff, 0x47,0x50, 0x4a,0x3, 0x4b,0xc0,
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0x4c,0x0, 0x4d,0x0, 0x4e,0xf, 0x5d,0x77,
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0x5c,0x0, 0x5f,0x33, 0x40,0x1
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0x25,0xc7, 0x26,0xc9, 0x27,0x7f, 0x29,0x00,
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0x2a,0x00, 0x2b,0xff, 0x2c,0x00, 0x2d,0xff,
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0x2e,0x00, 0x2f,0xff, 0x30,0x00, 0x31,0xff,
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0x32,0x00, 0x33,0xff, 0x34,0x00, 0x39,0xff,
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0x3a,0x00, 0x3b,0xff, 0x3c,0xff, 0x3d,0xff,
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0x3e,0x00, 0x3f,0xb0, 0x43,0xff, 0x44,0xff,
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0x46,0xff, 0x47,0x50, 0x4a,0x03, 0x4b,0xc0,
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0x4c,0x00, 0x4d,0x00, 0x4e,0x0f, 0x5d,0x77,
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0x5c,0x00, 0x5f,0x33, 0x40,0x01,
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};
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static void pnp_enter_ext_func_mode(device_t dev)
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@ -59,32 +56,39 @@ static void pnp_exit_ext_func_mode(device_t dev)
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outb(0xaa, dev->path.pnp.port);
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}
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static void vt1211_set_iobase(device_t dev, unsigned index, unsigned iobase)
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static void vt1211_set_iobase(device_t dev, u8 index, u16 iobase)
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{
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switch (dev->path.pnp.device) {
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case VT1211_FDC:
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case VT1211_PP:
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case VT1211_SP1:
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case VT1211_SP2:
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pnp_write_config(dev, index + 0, (iobase >> 2) & 0xff);
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break;
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case VT1211_HWM:
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default:
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pnp_write_config(dev, index + 0, (iobase >> 8) & 0xff);
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pnp_write_config(dev, index + 1, iobase & 0xff);
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break;
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case VT1211_FDC:
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case VT1211_PP:
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case VT1211_SP1:
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case VT1211_SP2:
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pnp_write_config(dev, index + 0, (iobase >> 2) & 0xff);
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break;
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case VT1211_ROM:
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/* TODO: Error. VT1211_ROM doesn't have an I/O base. */
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break;
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case VT1211_MIDI:
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case VT1211_GAME:
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case VT1211_GPIO:
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case VT1211_WDG:
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case VT1211_WUC:
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case VT1211_HWM:
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case VT1211_FIR:
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default:
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pnp_write_config(dev, index + 0, (iobase >> 8) & 0xff);
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pnp_write_config(dev, index + 1, iobase & 0xff);
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break;
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}
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}
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static void init_hwm(unsigned long base)
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/* Initialize VT1211 hardware monitor registers, which are at 0xECXX. */
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static void init_hwm(u16 base)
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{
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int i;
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/* initialize vt1211 hardware monitor registers, which are at 0xECXX */
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for(i = 0; i < sizeof(vt1211hwmonitorinits); i += 2) {
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outb(vt1211hwmonitorinits[i + 1],
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base + vt1211hwmonitorinits[i]);
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}
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for (i = 0; i < sizeof(hwm_io_regs); i += 2)
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outb(hwm_io_regs[i + 1], base + hwm_io_regs[i]);
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}
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static void vt1211_init(struct device *dev)
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@ -92,14 +96,10 @@ static void vt1211_init(struct device *dev)
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struct superio_via_vt1211_config *conf = dev->chip_info;
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struct resource *res0;
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if (!dev->enabled) {
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if (!dev->enabled)
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return;
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}
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switch (dev->path.pnp.device) {
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case VT1211_FDC:
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case VT1211_PP:
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break;
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case VT1211_SP1:
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res0 = find_resource(dev, PNP_IDX_IO0);
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init_uart8250(res0->base, &conf->com1);
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@ -112,14 +112,25 @@ static void vt1211_init(struct device *dev)
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res0 = find_resource(dev, PNP_IDX_IO0);
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init_hwm(res0->base);
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break;
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case VT1211_FDC:
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case VT1211_PP:
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case VT1211_MIDI:
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case VT1211_GAME:
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case VT1211_GPIO:
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case VT1211_WDG:
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case VT1211_WUC:
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case VT1211_FIR:
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case VT1211_ROM:
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/* TODO: Any init needed for these LDNs? */
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break;
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default:
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printk(BIOS_INFO, "vt1211 asked to initialise unknown device!\n");
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printk(BIOS_INFO, "VT1211: Cannot init unknown device!\n");
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}
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}
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static void vt1211_pnp_enable_resources(device_t dev)
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{
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printk(BIOS_DEBUG, "%s - enabling\n",dev_path(dev));
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printk(BIOS_DEBUG, "%s - enabling\n", dev_path(dev));
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pnp_enter_ext_func_mode(dev);
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pnp_enable_resources(dev);
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pnp_exit_ext_func_mode(dev);
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@ -130,41 +141,39 @@ static void vt1211_pnp_set_resources(struct device *dev)
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struct resource *res;
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#if CONFIG_CONSOLE_SERIAL8250 == 1
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if( dev->path.pnp.device == 2 ){
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for(res = dev->resource_list; res; res = res->next){
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/* TODO: Do the same for SP2? */
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if (dev->path.pnp.device == VT1211_SP1) {
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for (res = dev->resource_list; res; res = res->next) {
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res->flags |= IORESOURCE_STORED;
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report_resource_stored(dev, res, "");
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}
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return;
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}
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#endif
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pnp_enter_ext_func_mode(dev);
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/* Select the device */
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pnp_set_logical_device(dev);
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/* Paranoia says I should disable the device here... */
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for(res = dev->resource_list; res; res = res->next){
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for (res = dev->resource_list; res; res = res->next) {
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if (!(res->flags & IORESOURCE_ASSIGNED)) {
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printk(BIOS_ERR, "ERROR: %s %02lx %s size: 0x%010Lx not assigned\n",
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dev_path(dev), res->index,
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resource_type(res),
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res->size);
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printk(BIOS_ERR, "ERROR: %s %02lx %s size: 0x%010Lx "
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"not assigned\n", dev_path(dev), res->index,
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resource_type(res), res->size);
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continue;
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}
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/* Now store the resource */
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/* Now store the resource. */
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if (res->flags & IORESOURCE_IO) {
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vt1211_set_iobase(dev, res->index, res->base);
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}
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else if (res->flags & IORESOURCE_DRQ) {
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} else if (res->flags & IORESOURCE_DRQ) {
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pnp_set_drq(dev, res->index, res->base);
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}
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else if (res->flags & IORESOURCE_IRQ) {
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} else if (res->flags & IORESOURCE_IRQ) {
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pnp_set_irq(dev, res->index, res->base);
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}
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else {
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printk(BIOS_ERR, "ERROR: %s %02lx unknown resource type\n",
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dev_path(dev), res->index);
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} else {
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printk(BIOS_ERR, "ERROR: %s %02lx unknown resource "
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"type\n", dev_path(dev), res->index);
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return;
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}
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res->flags |= IORESOURCE_STORED;
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@ -177,12 +186,13 @@ static void vt1211_pnp_set_resources(struct device *dev)
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static void vt1211_pnp_enable(device_t dev)
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{
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if (!dev->enabled) {
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pnp_enter_ext_func_mode(dev);
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pnp_set_logical_device(dev);
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pnp_set_enable(dev, 0);
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pnp_exit_ext_func_mode(dev);
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}
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if (dev->enabled)
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return;
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pnp_enter_ext_func_mode(dev);
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pnp_set_logical_device(dev);
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pnp_set_enable(dev, 0);
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pnp_exit_ext_func_mode(dev);
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}
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struct device_operations ops = {
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@ -193,21 +203,25 @@ struct device_operations ops = {
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.init = vt1211_init,
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};
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/* TODO: Check if 0x07f8 is correct for FDC/PP/SP1/SP2, the rest is correct. */
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static struct pnp_info pnp_dev_info[] = {
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{ &ops, VT1211_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
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{ &ops, VT1211_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
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{ &ops, VT1211_SP1, PNP_IO0 | PNP_IRQ0, { 0x07f8, 0}, },
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{ &ops, VT1211_SP2, PNP_IO0 | PNP_IRQ0, { 0x07f8, 0}, },
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{ &ops, VT1211_HWM, PNP_IO0 , { 0xff00, 0 }, },
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{ &ops, VT1211_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0 }, },
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{ &ops, VT1211_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0 }, },
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{ &ops, VT1211_SP1, PNP_IO0 | PNP_IRQ0, { 0x07f8, 0 }, },
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{ &ops, VT1211_SP2, PNP_IO0 | PNP_IRQ0, { 0x07f8, 0 }, },
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{ &ops, VT1211_MIDI, PNP_IO0 | PNP_IRQ0, { 0xfffc, 0 }, },
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{ &ops, VT1211_GAME, PNP_IO0, { 0xfff8, 0 }, },
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{ &ops, VT1211_GPIO, PNP_IO0 | PNP_IRQ0, { 0xfff0, 0 }, },
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{ &ops, VT1211_WDG, PNP_IO0 | PNP_IRQ0, { 0xfff0, 0 }, },
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{ &ops, VT1211_WUC, PNP_IO0 | PNP_IRQ0, { 0xfff0, 0 }, },
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{ &ops, VT1211_HWM, PNP_IO0 | PNP_IRQ0, { 0xff00, 0 }, },
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{ &ops, VT1211_FIR, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0xff00, 0 }, },
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{ &ops, VT1211_ROM, },
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};
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static void enable_dev(struct device *dev)
|
||||
{
|
||||
printk(BIOS_DEBUG, "vt1211 enabling PNP devices.\n");
|
||||
pnp_enable_devices(dev,
|
||||
&ops,
|
||||
ARRAY_SIZE(pnp_dev_info),
|
||||
pnp_dev_info);
|
||||
pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
|
||||
}
|
||||
|
||||
struct chip_operations superio_via_vt1211_ops = {
|
||||
|
|
|
|||
|
|
@ -18,17 +18,16 @@
|
|||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
/* vt1211 PNP devices */
|
||||
|
||||
#define VT1211_FDC 0 /* Floppy */
|
||||
#define VT1211_PP 1 /* Parallel Port */
|
||||
#define VT1211_SP1 2 /* COM1 */
|
||||
#define VT1211_SP2 3 /* COM2 */
|
||||
#define VT1211_MIDI 6 /* MIDI */
|
||||
#define VT1211_GAME 7 /* Game port */
|
||||
#define VT1211_GPIO 8 /* GPIO pins */
|
||||
#define VT1211_WATCHDOG 9 /* Watchdog timer */
|
||||
#define VT1211_WAKEUP 10 /* Wakeup control */
|
||||
#define VT1211_HWM 11 /* Hardware monitor */
|
||||
#define VT1211_FIR 12 /* Irda */
|
||||
#define VT1211_ROM 13 /* ROM control */
|
||||
/* Logical device numbers (LDNs). */
|
||||
#define VT1211_FDC 0x00 /* Floppy */
|
||||
#define VT1211_PP 0x01 /* Parallel port */
|
||||
#define VT1211_SP1 0x02 /* COM1 */
|
||||
#define VT1211_SP2 0x03 /* COM2 */
|
||||
#define VT1211_MIDI 0x06 /* MIDI */
|
||||
#define VT1211_GAME 0x07 /* Game port (GMP) */
|
||||
#define VT1211_GPIO 0x08 /* GPIO */
|
||||
#define VT1211_WDG 0x09 /* Watchdog timer (WDG) */
|
||||
#define VT1211_WUC 0x0a /* Wake-up control (WUC) */
|
||||
#define VT1211_HWM 0x0b /* Hardware monitor (HM) */
|
||||
#define VT1211_FIR 0x0c /* Very fast IR (VFIR/FIR) */
|
||||
#define VT1211_ROM 0x0d /* Flash ROM */
|
||||
|
|
|
|||
Loading…
Reference in New Issue