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Currently flashrom assumes every vendor BIOS shares our view about which 

SPI opcodes should be placed in which location. Move to a less
optimistic implementation and actually use the generic SPI read
functions. They're useful for abstracting exactly this stuff and that
makes them the preferred choice.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3758 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Carl-Daniel Hailfinger 2008-11-18 00:43:14 +00:00
parent 7cb70d9abd
commit 8c0702b89b
1 changed files with 5 additions and 9 deletions
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14
util/flashrom/ichspi.c
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@ -300,7 +300,7 @@ static int ich7_run_opcode(OPCODE op, uint32_t offset,
if (op.atomic != 0) {
/* Select atomic command */
temp16 |= SPIC_ACS;
/* Selct prefix opcode */
/* Select prefix opcode */
if ((op.atomic - 1) == 1) {
/*Select prefix opcode 2 */
temp16 |= SPIC_SPOP;
@ -491,19 +491,15 @@ static int ich_spi_read_page(struct flashchip *flash, uint8_t * buf, int offset,
for (a = 0; a < page_size; a += maxdata) {
if (remaining < maxdata) {
if (run_opcode
(curopcodes->opcode[1],
offset + (page_size - remaining), remaining,
&buf[page_size - remaining]) != 0) {
if (spi_nbyte_read(offset + (page_size - remaining),
&buf[page_size - remaining], remaining)) {
printf_debug("Error reading");
return 1;
}
remaining = 0;
} else {
if (run_opcode
(curopcodes->opcode[1],
offset + (page_size - remaining), maxdata,
&buf[page_size - remaining]) != 0) {
if (spi_nbyte_read(offset + (page_size - remaining),
&buf[page_size - remaining], maxdata)) {
printf_debug("Error reading");
return 1;
}