Currently flashrom assumes every vendor BIOS shares our view about which
SPI opcodes should be placed in which location. Move to a less optimistic implementation and actually use the generic SPI read functions. They're useful for abstracting exactly this stuff and that makes them the preferred choice. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3758 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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@ -300,7 +300,7 @@ static int ich7_run_opcode(OPCODE op, uint32_t offset,
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if (op.atomic != 0) {
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if (op.atomic != 0) {
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/* Select atomic command */
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/* Select atomic command */
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temp16 |= SPIC_ACS;
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temp16 |= SPIC_ACS;
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/* Selct prefix opcode */
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/* Select prefix opcode */
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if ((op.atomic - 1) == 1) {
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if ((op.atomic - 1) == 1) {
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/*Select prefix opcode 2 */
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/*Select prefix opcode 2 */
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temp16 |= SPIC_SPOP;
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temp16 |= SPIC_SPOP;
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@ -491,19 +491,15 @@ static int ich_spi_read_page(struct flashchip *flash, uint8_t * buf, int offset,
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for (a = 0; a < page_size; a += maxdata) {
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for (a = 0; a < page_size; a += maxdata) {
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if (remaining < maxdata) {
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if (remaining < maxdata) {
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if (run_opcode
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if (spi_nbyte_read(offset + (page_size - remaining),
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(curopcodes->opcode[1],
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&buf[page_size - remaining], remaining)) {
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offset + (page_size - remaining), remaining,
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&buf[page_size - remaining]) != 0) {
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printf_debug("Error reading");
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printf_debug("Error reading");
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return 1;
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return 1;
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}
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}
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remaining = 0;
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remaining = 0;
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} else {
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} else {
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if (run_opcode
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if (spi_nbyte_read(offset + (page_size - remaining),
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(curopcodes->opcode[1],
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&buf[page_size - remaining], maxdata)) {
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offset + (page_size - remaining), maxdata,
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&buf[page_size - remaining]) != 0) {
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printf_debug("Error reading");
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printf_debug("Error reading");
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return 1;
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return 1;
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}
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}
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