util/ifdtool: Use -p platform name to detect IFDv2 platform and chipset
ifdtool uses `chipset` information to determine how certain straps are decoded. This has been used for IFDv1 platforms as well as IFDv2 platforms (CHIPSET_500_600_SERIES_TIGER_ALDER_POINT). IFDv2 platforms are all expected to pass in `-p` argument to identify the platform. This platform information can be used to identify the appropriate chipset information. For IFDv1 since `-p` argument is not provided, ifdtool needs to use certain fields in the descriptor (e.g. strap length) for unique identification of IFDv1 chipset. This change updates `check_ifd_version()` function to: 1. Determine if IFD version is v1 or v2 based on `-p` argument. If `-p` is not provided, it assumes that the platform is using IFDv1. 2. Based on IFD version, it calls either `ifd2_platform_to_chipset()` or `ifd1_guess_chipset()` to determine chipset information. This fixes the issue reported with CB:44815, where ifdtool is unable to identify Alder Lake chipsets. BUG=b:153888802 TEST=Able to dump FD contains correctly with platform quirks on Brya Platform. > ifdtool -d coreboot.rom -p adl PCH Revision: 500 series Tiger Point/ 600 series Alder Point Change-Id: I25f69ce775454409974056d8326c02e29038ec8a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54305 Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -69,9 +69,13 @@ static const char *const ich_chipset_names[] = {
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"8 series Wellsburg",
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"9 series Wildcat Point",
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"9 series Wildcat Point LP",
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"Apollo Lake: N3xxx, J3xxx",
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"Gemini Lake: N5xxx, J5xxx, N4xxx, J4xxx",
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"Jasper Lake: N6xxx, N51xx, N45xx",
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"Elkhart Lake: x6000 series Atom",
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"100/200 series Sunrise Point",
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"300 series Cannon Point/ 400 series Ice Point",
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"300 series Cannon Point",
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"400 series Ice Point",
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"500 series Tiger Point/ 600 series Alder Point",
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"C620 series Lewisburg",
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NULL
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@ -165,40 +169,16 @@ static fmsba_t *find_fmsba(char *image, int size)
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return PTR_IN_RANGE(fmsba, image, size) ? fmsba : NULL;
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}
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static enum ich_chipset guess_ifd_2_chipset(const fpsba_t *fpsba)
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{
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uint32_t pchstrp_22 = fpsba->pchstrp[22];
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uint32_t pchstrp_23 = fpsba->pchstrp[23];
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/* Offset 0x5B is the last PCH descriptor record */
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if (pchstrp_23 == 0xFFFFFFFF)
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return CHIPSET_N_J_SERIES;
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/* Offset 0x58 is PCH descriptor record is reserved */
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if (pchstrp_22 == 0x0)
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return CHIPSET_300_400_SERIES_CANNON_ICE_POINT;
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/* Offset 0x58 bit [2:0] is reserved 0x4 and 0x5a bit [7:0] is reserved 0x58 */
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if (((pchstrp_22 & 0x07) == 0x4) &&
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((pchstrp_22 & 0xFF0000) >> 16 == 0x58))
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return CHIPSET_500_600_SERIES_TIGER_ALDER_POINT;
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return CHIPSET_PCH_UNKNOWN;
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}
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/* port from flashrom */
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static enum ich_chipset guess_ich_chipset(const fdbar_t *fdb, const fpsba_t *fpsba)
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static enum ich_chipset ifd1_guess_chipset(char *image, int size)
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{
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const fdbar_t *fdb = find_fd(image, size);
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if (!fdb)
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exit(EXIT_FAILURE);
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uint32_t iccriba = (fdb->flmap2 >> 16) & 0xff;
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uint32_t msl = (fdb->flmap2 >> 8) & 0xff;
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uint32_t isl = (fdb->flmap1 >> 24);
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uint32_t nm = (fdb->flmap1 >> 8) & 0x7;
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int temp_chipset;
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/* Check for IFD2 chipset type */
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temp_chipset = guess_ifd_2_chipset(fpsba);
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if (temp_chipset != CHIPSET_PCH_UNKNOWN)
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return temp_chipset;
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/* Rest for IFD1 chipset type */
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if (iccriba == 0x00) {
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@ -228,6 +208,27 @@ static enum ich_chipset guess_ich_chipset(const fdbar_t *fdb, const fpsba_t *fps
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}
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}
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static enum ich_chipset ifd2_platform_to_chipset(const int pindex)
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{
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switch (pindex) {
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case PLATFORM_GLK:
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return CHIPSET_N_J_SERIES_GEMINI_LAKE;
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case PLATFORM_JSL:
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return CHIPSET_N_SERIES_JASPER_LAKE;
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case PLATFORM_EHL:
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return CHIPSET_x6000_SERIES_ELKHART_LAKE;
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case PLATFORM_CNL:
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return CHIPSET_300_SERIES_CANNON_POINT;
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case PLATFORM_TGL:
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case PLATFORM_ADL:
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return CHIPSET_500_600_SERIES_TIGER_ALDER_POINT;
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case PLATFORM_ICL:
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return CHIPSET_400_SERIES_ICE_POINT;
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default:
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return CHIPSET_PCH_UNKNOWN;
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}
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}
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/*
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* Some newer platforms have re-defined the FCBA field that was used to
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* distinguish IFD v1 v/s v2. Define a list of platforms that we know do not
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@ -255,50 +256,17 @@ static int is_platform_ifd_2(void)
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return 0;
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}
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/*
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* There is no version field in the descriptor so to determine
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* if this is a new descriptor format we check the hardcoded SPI
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* read frequency to see if it is fixed at 20MHz or 17MHz.
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*/
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static int get_ifd_version_from_fcba(char *image, int size)
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{
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int read_freq;
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const fcba_t *fcba = find_fcba(image, size);
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const fdbar_t *fdb = find_fd(image, size);
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const fpsba_t *fpsba = find_fpsba(image, size);
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if (!fcba || !fdb || !fpsba)
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exit(EXIT_FAILURE);
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chipset = guess_ich_chipset(fdb, fpsba);
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/* TODO: port ifd_version and max_regions
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* against guess_ich_chipset()
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*/
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read_freq = (fcba->flcomp >> 17) & 7;
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switch (read_freq) {
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case SPI_FREQUENCY_20MHZ:
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return IFD_VERSION_1;
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case SPI_FREQUENCY_17MHZ:
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case SPI_FREQUENCY_50MHZ_30MHZ:
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return IFD_VERSION_2;
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default:
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fprintf(stderr, "Unknown descriptor version: %d\n",
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read_freq);
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exit(EXIT_FAILURE);
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}
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}
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static void check_ifd_version(char *image, int size)
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{
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if (is_platform_ifd_2())
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if (is_platform_ifd_2()) {
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ifd_version = IFD_VERSION_2;
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else
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ifd_version = get_ifd_version_from_fcba(image, size);
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if (ifd_version == IFD_VERSION_1)
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max_regions = MAX_REGIONS_OLD;
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else
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chipset = ifd2_platform_to_chipset(platform);
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max_regions = MAX_REGIONS;
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} else {
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ifd_version = IFD_VERSION_1;
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chipset = ifd1_guess_chipset(image, size);
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max_regions = MAX_REGIONS_OLD;
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}
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}
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static region_t get_region(const frba_t *frba, unsigned int region_type)
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@ -35,9 +35,13 @@ enum ich_chipset {
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CHIPSET_8_SERIES_WELLSBURG,
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CHIPSET_9_SERIES_WILDCAT_POINT,
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CHIPSET_9_SERIES_WILDCAT_POINT_LP,
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CHIPSET_N_J_SERIES, /* Gemini Lake: N5xxx, J5xxx, N4xxx, J4xxx */
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CHIPSET_N_J_SERIES_APOLLO_LAKE, /* Apollo Lake: N3xxx, J3xxx */
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CHIPSET_N_J_SERIES_GEMINI_LAKE, /* Gemini Lake: N5xxx, J5xxx, N4xxx, J4xxx */
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CHIPSET_N_SERIES_JASPER_LAKE, /* Jasper Lake: N6xxx, N51xx, N45xx */
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CHIPSET_x6000_SERIES_ELKHART_LAKE, /* Elkhart Lake: x6000 */
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CHIPSET_100_200_SERIES_SUNRISE_POINT, /* 6th-7th gen Core i/o (LP) variants */
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CHIPSET_300_400_SERIES_CANNON_ICE_POINT, /* 8th-10th gen Core i/o (LP) variants */
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CHIPSET_300_SERIES_CANNON_POINT, /* 8th-9th gen Core i/o (LP) variants */
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CHIPSET_400_SERIES_ICE_POINT, /* 10th gen Core i/o (LP) variants */
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CHIPSET_500_600_SERIES_TIGER_ALDER_POINT, /* 11th-12th gen Core i/o (LP)
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* variants onwards */
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CHIPSET_C620_SERIES_LEWISBURG,
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