diff --git a/src/soc/intel/cannonlake/acpi/gpio_op.asl b/src/soc/intel/cannonlake/acpi/gpio_op.asl
index 7f2a40cd46..9fa3dc4a86 100644
--- a/src/soc/intel/cannonlake/acpi/gpio_op.asl
+++ b/src/soc/intel/cannonlake/acpi/gpio_op.asl
@@ -1,4 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
+#include <intelblocks/gpio_defs.h>
 
 /*
  * Get GPIO Value
@@ -11,7 +12,7 @@ Method (GRXS, 1, Serialized)
 	{
 		VAL0, 32
 	}
-	Local0 = GPIORXSTATE_MASK & (VAL0 >> GPIORXSTATE_SHIFT)
+	Local0 = (PAD_CFG0_RX_STATE & VAL0) >> PAD_CFG0_RX_STATE_BIT
 
 	Return (Local0)
 }
@@ -27,7 +28,7 @@ Method (GTXS, 1, Serialized)
 	{
 		VAL0, 32
 	}
-	Local0 = GPIOTXSTATE_MASK & VAL0
+	Local0 = PAD_CFG0_TX_STATE & VAL0
 
 	Return (Local0)
 }
@@ -43,7 +44,7 @@ Method (STXS, 1, Serialized)
 	{
 		VAL0, 32
 	}
-	VAL0 |= GPIOTXSTATE_MASK
+	VAL0 |= PAD_CFG0_TX_STATE
 }
 
 /*
@@ -57,7 +58,7 @@ Method (CTXS, 1, Serialized)
 	{
 		VAL0, 32
 	}
-	VAL0 &= ~GPIOTXSTATE_MASK
+	VAL0 &= ~PAD_CFG0_TX_STATE
 }
 
 /*
@@ -76,8 +77,8 @@ Method (GPMO, 2, Serialized)
 	{
 		VAL0, 32
 	}
-	Local0 = ~GPIOPADMODE_MASK & VAL0
-	Arg1 = (Arg1 << GPIOPADMODE_SHIFT) & GPIOPADMODE_MASK
+	Local0 = ~PAD_CFG0_MODE_MASK & VAL0
+	Arg1 = (Arg1 << PAD_CFG0_MODE_SHIFT) & PAD_CFG0_MODE_MASK
 	VAL0 = Local0 | Arg1
 }
 
@@ -97,9 +98,9 @@ Method (GTXE, 2, Serialized)
 	}
 
 	If (Arg1 == 1) {
-		VAL0 &= ~GPIOTXBUFDIS_MASK
+		VAL0 &= ~PAD_CFG0_TX_DISABLE
 	} ElseIf (Arg1 == 0){
-		VAL0 |= GPIOTXBUFDIS_MASK
+		VAL0 |= PAD_CFG0_TX_DISABLE
 	}
 }
 
@@ -119,8 +120,8 @@ Method (GRXE, 2, Serialized)
 	}
 
 	If (Arg1 == 1) {
-		VAL0 &= ~GPIORXBUFDIS_MASK
+		VAL0 &= ~PAD_CFG0_RX_DISABLE
 	} ElseIf (Arg1 == 0){
-		VAL0 |= GPIORXBUFDIS_MASK
+		VAL0 |= PAD_CFG0_RX_DISABLE
 	}
 }
diff --git a/src/soc/intel/cannonlake/include/soc/gpio_common.h b/src/soc/intel/cannonlake/include/soc/gpio_common.h
deleted file mode 100644
index c11ef50403..0000000000
--- a/src/soc/intel/cannonlake/include/soc/gpio_common.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-#ifndef _SOC_CANNONLAKE_GPIO_COMMON_H_
-#define _SOC_CANNONLAKE_GPIO_COMMON_H_
-
-#define GPIORXSTATE_MASK			0x1
-#define GPIORXSTATE_SHIFT			1
-#define GPIOTXSTATE_MASK			0x1
-#define GPIOPADMODE_MASK			0xC00
-#define GPIOPADMODE_SHIFT			10
-#define GPIOTXBUFDIS_MASK			0x100
-#define GPIORXBUFDIS_MASK			0x200
-
-#endif
diff --git a/src/soc/intel/cannonlake/include/soc/gpio_defs.h b/src/soc/intel/cannonlake/include/soc/gpio_defs.h
index 9b1690ea9d..e7769b5f31 100644
--- a/src/soc/intel/cannonlake/include/soc/gpio_defs.h
+++ b/src/soc/intel/cannonlake/include/soc/gpio_defs.h
@@ -6,7 +6,6 @@
 #ifndef __ACPI__
 #include <stddef.h>
 #endif
-#include <soc/gpio_common.h>
 #include <soc/gpio_soc_defs.h>
 
 #define GPIO_NUM_PAD_CFG_REGS   4 /* DW0, DW1, DW2, DW3 */
diff --git a/src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h b/src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h
index a1f51d1d97..bd68b04f9b 100644
--- a/src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h
+++ b/src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h
@@ -6,7 +6,6 @@
 #ifndef __ACPI__
 #include <stddef.h>
 #endif
-#include <soc/gpio_common.h>
 #include <soc/gpio_soc_defs_cnp_h.h>
 
 #define GPIO_NUM_PAD_CFG_REGS   4 /* DW0, DW1, DW2, DW3 */