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vc/amd/fsp/phoenix/FspUsb: update USB config struct for Phoenix SoC 

Phoenix has one more Type C port and two more USB2 ports which are used
as the legacy USB part of the two USB4 ports. The USB struct version
numbers have also changed, since it's a newer and incompatible version
of that struct.

TEST=After changing FSP to not hard-code the USB PHY config, but use the
configuration provided by coreboot, and applying this patch, the USB
connector on the USB2 port 4 lines works.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If52934595dd612154b97e7b90dbd96243146017a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73379
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Felix Held 2023-03-02 16:40:29 +01:00
parent 8414eed5a0
commit 8c119079d1
3 changed files with 63 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

29
src/mainboard/amd/birman/devicetree_phoenix.cb
View File

@ -127,6 +127,34 @@ chip soc/amd/phoenix
.txhsxvtune = 0x3,
.txrestune = 0x2,
},
.Usb2PhyPort[6] = {
.compdistune = 0x3,
.pllbtune = 0x1,
.pllitune = 0x0,
.pllptune = 0xe,
.sqrxtune = 0x3,
.txfslstune = 0x3,
.txpreempamptune = 0x2,
.txpreemppulsetune = 0x0,
.txrisetune = 0x1,
.txvreftune = 0x3,
.txhsxvtune = 0x3,
.txrestune = 0x2,
},
.Usb2PhyPort[7] = {
.compdistune = 0x3,
.pllbtune = 0x1,
.pllitune = 0x0,
.pllptune = 0xe,
.sqrxtune = 0x3,
.txfslstune = 0x3,
.txpreempamptune = 0x2,
.txpreemppulsetune = 0x0,
.txrisetune = 0x1,
.txvreftune = 0x3,
.txhsxvtune = 0x3,
.txrestune = 0x2,
},
.Usb3PhyPort[0] = {
.tx_term_ctrl = 0x2,
.rx_term_ctrl = 0x2,
@ -147,6 +175,7 @@ chip soc/amd/phoenix
},
.ComboPhyStaticConfig[0] = USB_COMBO_PHY_MODE_USB_C,
.ComboPhyStaticConfig[1] = USB_COMBO_PHY_MODE_USB_C,
.ComboPhyStaticConfig[2] = USB_COMBO_PHY_MODE_USB_C,
.BatteryChargerEnable = 0,
.PhyP3CpmP4Support = 0,
}"

29
src/mainboard/amd/mayan/devicetree_phoenix.cb
View File

@ -127,6 +127,34 @@ chip soc/amd/phoenix
.txhsxvtune = 0x3,
.txrestune = 0x2,
},
.Usb2PhyPort[6] = {
.compdistune = 0x3,
.pllbtune = 0x1,
.pllitune = 0x0,
.pllptune = 0xe,
.sqrxtune = 0x3,
.txfslstune = 0x3,
.txpreempamptune = 0x2,
.txpreemppulsetune = 0x0,
.txrisetune = 0x1,
.txvreftune = 0x3,
.txhsxvtune = 0x3,
.txrestune = 0x2,
},
.Usb2PhyPort[7] = {
.compdistune = 0x3,
.pllbtune = 0x1,
.pllitune = 0x0,
.pllptune = 0xe,
.sqrxtune = 0x3,
.txfslstune = 0x3,
.txpreempamptune = 0x2,
.txpreemppulsetune = 0x0,
.txrisetune = 0x1,
.txvreftune = 0x3,
.txhsxvtune = 0x3,
.txrestune = 0x2,
},
.Usb3PhyPort[0] = {
.tx_term_ctrl = 0x2,
.rx_term_ctrl = 0x2,
@ -147,6 +175,7 @@ chip soc/amd/phoenix
},
.ComboPhyStaticConfig[0] = USB_COMBO_PHY_MODE_USB_C,
.ComboPhyStaticConfig[1] = USB_COMBO_PHY_MODE_USB_C,
.ComboPhyStaticConfig[2] = USB_COMBO_PHY_MODE_USB_C,
.BatteryChargerEnable = 0,
.PhyP3CpmP4Support = 0,
}"

12
src/vendorcode/amd/fsp/phoenix/FspUsb.h
View File

@ -1,16 +1,14 @@
#ifndef __FSPUSB_H__
#define __FSPUSB_H__
/* TODO: Update for Phoenix */
#include <FspUpd.h>
#define FSP_USB_STRUCT_MAJOR_VERSION 0xd
#define FSP_USB_STRUCT_MINOR_VERSION 0xe
#define FSP_USB_STRUCT_MAJOR_VERSION 0xf
#define FSP_USB_STRUCT_MINOR_VERSION 0x1
#define USB2_PORT_COUNT 6
#define USB2_PORT_COUNT 8
#define USB3_PORT_COUNT 3
#define USBC_COMBO_PHY_COUNT 2
#define USBC_COMBO_PHY_COUNT 3
struct fch_usb2_phy {
uint8_t compdistune; ///< COMPDISTUNE
@ -58,7 +56,7 @@ struct usb_phy_config {
uint8_t BatteryChargerEnable; ///< bit[1:0]-Usb0 Port[1:0], bit[3:2]-Usb1 Port[1:0]
uint8_t PhyP3CpmP4Support; ///< bit[1:0]-Usb0 Port[1:0], bit[3:2]-Usb1 Port[1:0]
uint8_t ComboPhyStaticConfig[USBC_COMBO_PHY_COUNT]; ///< 0-Type C, 1- USB only mode, 2- DP only mode, 3- USB + DP
uint8_t Reserved2[4];
uint8_t Reserved2[3];
} __packed;
#endif