From 8c127ecc3c28a3188490af8daef43d528560ebd2 Mon Sep 17 00:00:00 2001 From: Jeremy Compostella Date: Thu, 2 Feb 2023 16:53:50 -0700 Subject: [PATCH] soc/intel/alderlake: Add a missing RPL-P power limits configuration This patch adds the {MCH:a706, TDP:28W} missing 28W configuration. BUG=b:267666609 BRANCH=firmware-brya-14505.B TEST=Power Limit are properly set on skolas 28W Change-Id: Ice35d622eeec5799c53de086430d00dc8789097e Signed-off-by: Jeremy Compostella Reviewed-on: https://review.coreboot.org/c/coreboot/+/72734 Tested-by: build bot (Jenkins) Reviewed-by: Sumeet R Pawnikar Reviewed-by: Tarun Tuli Reviewed-by: Nick Vaccaro --- src/soc/intel/alderlake/chip.h | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index 5173b1cf03..8e76e555ec 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -133,6 +133,7 @@ static const struct { { PCI_DID_INTEL_ADL_S_ID_12, ADL_S_202_35W_CORE, TDP_35W }, { PCI_DID_INTEL_ADL_S_ID_12, ADL_S_202_46W_CORE, TDP_46W }, { PCI_DID_INTEL_RPL_P_ID_1, RPL_P_682_642_482_45W_CORE, TDP_45W }, + { PCI_DID_INTEL_RPL_P_ID_1, RPL_P_682_482_282_28W_CORE, TDP_28W }, { PCI_DID_INTEL_RPL_P_ID_2, RPL_P_682_482_282_28W_CORE, TDP_28W }, { PCI_DID_INTEL_RPL_P_ID_3, RPL_P_282_242_142_15W_CORE, TDP_15W }, { PCI_DID_INTEL_RPL_P_ID_4, RPL_P_282_242_142_15W_CORE, TDP_15W },