From 8c178910221ea59936dd31644bde68a66d586dce Mon Sep 17 00:00:00 2001
From: Felix Held <felix-coreboot@felixheld.de>
Date: Thu, 7 Sep 2023 16:01:22 +0200
Subject: [PATCH] soc/amd/cezanne,common: expose eMMC device in ACPI when
 enabled

When the eMMC MMIO device is enabled in the devicetree, it needs to be
exposed in ACPI in order for the OS driver to be able to attach to it.
The Cezanne eMMC controller isn't used in google/guybrush, so this the
code path where the eMMC MMIO device is enabled in the devicetree can't
be easily tested.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I69ff79b2d1c6a08cf333a2bb3996931962c2c102
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77989
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
---
 src/soc/amd/cezanne/acpi/mmio.asl    | 36 ++++++++++++++++++++++++++++
 src/soc/amd/common/block/emmc/emmc.c | 15 ++++++++++++
 2 files changed, 51 insertions(+)

diff --git a/src/soc/amd/cezanne/acpi/mmio.asl b/src/soc/amd/cezanne/acpi/mmio.asl
index 930ca169d3..c138cbcb03 100644
--- a/src/soc/amd/cezanne/acpi/mmio.asl
+++ b/src/soc/amd/cezanne/acpi/mmio.asl
@@ -58,6 +58,42 @@ Device (GPIO)
 	}
 }
 
+Device (MMC0)
+{
+	Name (_HID, "AMDI0040")
+	Name (_UID, 0x0)
+	Method (_CRS, 0) {
+		Local0 = ResourceTemplate() {
+			Interrupt (
+				ResourceConsumer,
+				Level,
+				ActiveLow,
+				Exclusive, , , IRQR)
+			{ 0 }
+			Memory32Fixed (ReadWrite, APU_EMMC_BASE, 0x1000)
+		}
+		CreateDWordField (Local0, IRQR._INT, IRQN)
+		If (PICM) {
+			IRQN = IMMC
+		} Else {
+			IRQN = PMMC
+		}
+		If (IRQN == 0x1f) {
+			Return (ResourceTemplate(){
+				Memory32Fixed (ReadWrite, APU_EMMC_BASE, 0x1000)
+			})
+		} Else {
+			Return (Local0)
+		}
+	}
+
+	Name (STAT, 0x0)
+	Method (_STA, 0x0, NotSerialized)
+	{
+		Return (STAT)
+	}
+}
+
 Device (FUR0)
 {
 	Name (_HID, "AMDI0020")
diff --git a/src/soc/amd/common/block/emmc/emmc.c b/src/soc/amd/common/block/emmc/emmc.c
index a068031a4f..09d235076c 100644
--- a/src/soc/amd/common/block/emmc/emmc.c
+++ b/src/soc/amd/common/block/emmc/emmc.c
@@ -1,5 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <acpi/acpigen.h>
 #include <amdblocks/aoac.h>
 #include <device/device.h>
 #include <soc/aoac_defs.h>
@@ -15,9 +16,23 @@ static void emmc_enable(struct device *dev)
 		power_off_aoac_device(FCH_AOAC_DEV_EMMC);
 }
 
+static const char *emmc_acpi_name(const struct device *dev)
+{
+	return "MMC0";
+}
+
+static void emmc_acpi_fill_ssdt(const struct device *dev)
+{
+	acpigen_write_scope(acpi_device_path(dev));
+	acpigen_write_store_int_to_namestr(acpi_device_status(dev), "STAT");
+	acpigen_pop_len(); /* Scope */
+}
+
 struct device_operations amd_emmc_mmio_ops = {
 	.read_resources = emmc_read_resources,
 	.set_resources = noop_set_resources,
 	.scan_bus = scan_static_bus,
 	.enable = emmc_enable,
+	.acpi_name = emmc_acpi_name,
+	.acpi_fill_ssdt = emmc_acpi_fill_ssdt,
 };