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broadwell: sata updates from 2.1.0 ref code 

fixed a coding error and sync sata configuration with ref code

BUG=chrome-os-partner:28234
BRANCH=None
TEST=build and boot on samus
     verify registers between samus and crb

Original-Change-Id: I09dd80a9772ac82b841363a540c9b7a8689e04a9
Original-Signed-off-by: Kane Chen <kane.chen@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/213137
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
(cherry picked from commit 0fbb59e3c5117a513ef19117560bb41dfe8c0d71)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I99a389b06f4ec077c298100ca878c68ef69debfa
Reviewed-on: http://review.coreboot.org/8959
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
This commit is contained in:
Kane Chen 2014-08-19 10:51:46 -07:00 committed by Marc Jones
parent 1b0d5a3c17
commit 8c1fd78134
1 changed files with 8 additions and 14 deletions
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22
src/soc/intel/broadwell/sata.c
View File

@ -60,19 +60,8 @@ static void sata_init(struct device *dev)
pci_write_config8(dev, PCI_INTERRUPT_LINE, 0x0a); pci_write_config8(dev, PCI_INTERRUPT_LINE, 0x0a);
/* Set timings */ /* Set timings */
pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE);
IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS | pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE);
IDE_PPE0 | IDE_IE0 | IDE_TIME0);
pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS);
/* Sync DMA */
pci_write_config16(dev, IDE_SDMA_CNT, IDE_PSDE0);
pci_write_config16(dev, IDE_SDMA_TIM, 0x0001);
/* Set IDE I/O Configuration */
reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0;
pci_write_config32(dev, IDE_CONFIG, reg32);
/* for AHCI, Port Enable is managed in memory mapped space */ /* for AHCI, Port Enable is managed in memory mapped space */
reg16 = pci_read_config16(dev, 0x92); reg16 = pci_read_config16(dev, 0x92);
@ -82,7 +71,7 @@ static void sata_init(struct device *dev)
udelay(2); udelay(2);
/* Setup register 98h */ /* Setup register 98h */
reg32 = pci_read_config16(dev, 0x98); reg32 = pci_read_config32(dev, 0x98);
reg32 &= ~((1 << 31) | (1 << 30)); reg32 &= ~((1 << 31) | (1 << 30));
reg32 |= 1 << 23; reg32 |= 1 << 23;
reg32 |= 1 << 24; /* Enable MPHY Dynamic Power Gating */ reg32 |= 1 << 24; /* Enable MPHY Dynamic Power Gating */
@ -212,6 +201,11 @@ static void sata_init(struct device *dev)
reg32 |= (1 << 17) | (1 << 16) | (1 << 19); reg32 |= (1 << 17) | (1 << 16) | (1 << 19);
reg32 |= (1 << 31) | (1 << 30) | (1 << 29); reg32 |= (1 << 31) | (1 << 30) | (1 << 29);
pci_write_config32(dev, 0x300, reg32); pci_write_config32(dev, 0x300, reg32);
/* Register Lock */
reg32 = pci_read_config32(dev, 0x9c);
reg32 |= (1 << 31);
pci_write_config32(dev, 0x9c, reg32);
} }
/* /*