rockchip: rk3288: multiple NPLL rate in pll_para_config
Due to HDMI need to set dclk_rate to 27Mhz, and we can't caclu a suitable config paramters for this rate, so we need to multiple rate unless the vco larger then VCO_MAX. When NPLL rate multiple to 54MHz, pll_para_config could caclu a right paramters, and I have verify the clock jitter is okay to HDMI output. Jitter Reports: Dclk Rate NPLL Rate nr/no/nf jitter Margin 27MHz 54MHz 2/10/45 449.0ps +51.0% BRANCH=None BUG=chrome-os-partner:42946 TEST=Mickey board, show right recovery picture on TV, and 480p clock jitter test passed Change-Id: Iaa0a6622e63d88918ed465900e630bdf16fde706 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Commit-Id: 59f1552026889f61167cfeaec3def668ba709c10 Original-Signed-off-by: Yakir Yang <ykk@rock-chips.com> Original-Change-Id: Iab274b41f163d2d61332df13e5091f0b605cb65c Original-Reviewed-on: https://chromium-review.googlesource.com/288416 Original-Commit-Queue: David Hendricks <dhendrix@chromium.org> Original-Tested-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290331 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/11393 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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@ -498,7 +498,7 @@ void rkclk_configure_tsadc(unsigned int hz)
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RK_CLRSETBITS(0x3f << 0, (div - 1) << 0));
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}
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static int pll_para_config(u32 freq_hz, struct pll_div *div)
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static int pll_para_config(u32 freq_hz, struct pll_div *div, u32 *ext_div)
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{
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u32 ref_khz = OSC_HZ / KHz, nr, nf = 0;
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u32 fref_khz;
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@ -512,17 +512,27 @@ static int pll_para_config(u32 freq_hz, struct pll_div *div)
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printk(BIOS_ERR, "%s: the frequency can not be 0 Hz\n", __func__);
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return -1;
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}
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no = div_round_up(VCO_MIN_KHZ, freq_khz);
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if (ext_div) {
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*ext_div = div_round_up(no, max_no);
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no = div_round_up(no, *ext_div);
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}
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/* only even divisors (and 1) are supported */
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if (no > 1)
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no = div_round_up(no, 2) * 2;
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vco_khz = freq_khz * no;
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if (ext_div)
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vco_khz *= *ext_div;
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if (vco_khz < VCO_MIN_KHZ || vco_khz > VCO_MAX_KHZ || no > max_no) {
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printk(BIOS_ERR, "%s: Cannot find out a supported VCO"
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" for Frequency (%uHz).\n", __func__, freq_hz);
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return -1;
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}
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div->no = no;
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best_diff_khz = vco_khz;
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@ -608,8 +618,9 @@ void rkclk_configure_vop_aclk(u32 vop_id, u32 aclk_hz)
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int rkclk_configure_vop_dclk(u32 vop_id, u32 dclk_hz)
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{
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struct pll_div npll_config = {0};
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u32 lcdc_div;
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if (pll_para_config(dclk_hz, &npll_config))
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if (pll_para_config(dclk_hz, &npll_config, &lcdc_div))
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return -1;
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/* npll enter slow-mode */
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@ -633,12 +644,14 @@ int rkclk_configure_vop_dclk(u32 vop_id, u32 dclk_hz)
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switch (vop_id) {
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case 0:
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write32(&cru_ptr->cru_clksel_con[27],
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RK_CLRSETBITS(0xff << 8 | 3 << 0, 0 << 8 | 2 << 0));
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RK_CLRSETBITS(0xff << 8 | 3 << 0,
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(lcdc_div - 1) << 8 | 2 << 0));
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break;
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case 1:
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write32(&cru_ptr->cru_clksel_con[29],
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RK_CLRSETBITS(0xff << 8 | 3 << 6, 0 << 8 | 2 << 6));
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RK_CLRSETBITS(0xff << 8 | 3 << 6,
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(lcdc_div - 1) << 8 | 2 << 6));
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break;
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}
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return 0;
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