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soc/intel/alderlake: Disable L1 substates for PCIe compliance test mode 

Disable L1 substates for PCIe compliance test mode in order to get
continuous clock output.

BUG=b:235863379
TEST=Boot in compliance mode, check FSP settings

Signed-off-by: Bora Guvendik <bora.guvendik@intel.corp-partner.google.com>
Change-Id: I2a3b313425e00fe11f616d964f825baaef463c71
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70165
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
This commit is contained in:
Bora Guvendik 2022-11-29 15:45:06 -08:00 committed by Martin L Roth
parent 447f5777aa
commit 8c46232005
1 changed files with 3 additions and 1 deletions
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4
src/soc/intel/alderlake/fsp_params.c
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@ -471,7 +471,9 @@ static const SI_PCH_DEVICE_INTERRUPT_CONFIG *pci_irq_to_fsp(size_t *out_count)
*/ */
static int get_l1_substate_control(enum L1_substates_control ctl) static int get_l1_substate_control(enum L1_substates_control ctl)
{ {
if ((ctl > L1_SS_L1_2) || (ctl == L1_SS_FSP_DEFAULT)) if (CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE))
ctl = L1_SS_DISABLED;
else if ((ctl > L1_SS_L1_2) || (ctl == L1_SS_FSP_DEFAULT))
ctl = L1_SS_L1_2; ctl = L1_SS_L1_2;
return ctl - 1; return ctl - 1;
} }