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Cosmetic cleanup. 

Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6594 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Scott Duplichan 2011-05-15 22:10:15 +00:00 committed by Marc Jones
parent 5d878ad312
commit 8c46263721
5 changed files with 6 additions and 37 deletions
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11
src/cpu/amd/agesa_wrapper/family14/model_14_init.c
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@ -31,7 +31,6 @@
#include <cpu/cpu.h> #include <cpu/cpu.h>
#include <cpu/x86/cache.h> #include <cpu/x86/cache.h>
#include <cpu/x86/mtrr.h> #include <cpu/x86/mtrr.h>
#include <cpu/amd/multicore.h>
#include <cpu/amd/amdfam14.h> #include <cpu/amd/amdfam14.h>
#define MCI_STATUS 0x401 #define MCI_STATUS 0x401
@ -58,19 +57,15 @@ void wrmsr_amd(u32 index, msr_t msr)
static void model_14_init(device_t dev) static void model_14_init(device_t dev)
{ {
printk(BIOS_DEBUG, "Model 14 Init - a no-op.\n"); printk(BIOS_DEBUG, "Model 14 Init.\n");
u8 i; u8 i;
msr_t msr; msr_t msr;
int msrno; int msrno;
struct node_core_id id;
#if CONFIG_LOGICAL_CPUS == 1 #if CONFIG_LOGICAL_CPUS == 1
u32 siblings; u32 siblings;
#endif #endif
// id = get_node_core_id(read_nb_cfg_54()); /* nb_cfg_54 can not be set */
// printk(BIOS_DEBUG, "nodeid = %02d, coreid = %02d\n", id.nodeid, id.coreid);
disable_cache (); disable_cache ();
/* Enable access to AMD RdDram and WrDram extension bits */ /* Enable access to AMD RdDram and WrDram extension bits */
msr = rdmsr(SYSCFG_MSR); msr = rdmsr(SYSCFG_MSR);
@ -100,10 +95,6 @@ static void model_14_init(device_t dev)
/* Enable the local cpu apics */ /* Enable the local cpu apics */
setup_lapic(); setup_lapic();
/* Set the processor name string */
// init_processor_name();
#if CONFIG_LOGICAL_CPUS == 1 #if CONFIG_LOGICAL_CPUS == 1
siblings = cpuid_ecx(0x80000008) & 0xff; siblings = cpuid_ecx(0x80000008) & 0xff;

7
src/include/cpu/amd/amdfam14.h
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@ -36,18 +36,11 @@
msr_t rdmsr_amd(u32 index); msr_t rdmsr_amd(u32 index);
void wrmsr_amd(u32 index, msr_t msr); void wrmsr_amd(u32 index, msr_t msr);
//#if defined(__GNUC__)
//// it can be used to get unitid and coreid it running only
//struct node_core_id get_node_core_id(u32 nb_cfg_54);
//struct node_core_id get_node_core_id_x(void);
//#endif
#if defined(__PRE_RAM__) #if defined(__PRE_RAM__)
void wait_all_core0_started(void); void wait_all_core0_started(void);
void wait_all_other_cores_started(u32 bsp_apicid); void wait_all_other_cores_started(u32 bsp_apicid);
void wait_all_aps_started(u32 bsp_apicid); void wait_all_aps_started(u32 bsp_apicid);
void allow_all_aps_stop(u32 bsp_apicid); void allow_all_aps_stop(u32 bsp_apicid);
#endif #endif
u32 get_initial_apicid(void);
#endif /* CPU_AMD_FAM14_H */ #endif /* CPU_AMD_FAM14_H */

18
src/mainboard/amd/persimmon/get_bus_conf.c
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@ -42,25 +42,12 @@ u32 pci1234x[] = {
0x0000ff0, 0x0000ff0,
}; };
/*
* HT Chain device num, actually it is unit id base of every ht device in chain,
* assume every chain only have 4 ht device at most
*/
u32 hcdnx[] = {
0x20202020,
};
u32 bus_type[256]; u32 bus_type[256];
u32 sbdn_sb800; u32 sbdn_sb800;
//KZ [092110]extern void get_pci1234(void);
static u32 get_bus_conf_done = 0; static u32 get_bus_conf_done = 0;
void get_bus_conf(void) void get_bus_conf(void)
{ {
u32 apicid_base; u32 apicid_base;
@ -139,8 +126,5 @@ void get_bus_conf(void)
/* I/O APICs: APIC ID Version State Address */ /* I/O APICs: APIC ID Version State Address */
bus_isa = 10; bus_isa = 10;
apicid_base = CONFIG_MAX_CPUS; apicid_base = CONFIG_MAX_CPUS;
//#if CONFIG_LOGICAL_CPUS==1 apicid_sb800 = apicid_base;
// apicid_base = get_apicid_base(1);
//#endif
apicid_sb800 = apicid_base + 0;
} }

5
src/mainboard/amd/persimmon/mainboard.c
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@ -53,7 +53,8 @@ uint64_t uma_memory_base, uma_memory_size;
*************************************************/ *************************************************/
static void persimmon_enable(device_t dev) static void persimmon_enable(device_t dev)
{ {
printk(BIOS_INFO, "Mainboard Persimmon Enable. dev=0x%p\n", dev); printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
#if (CONFIG_GFXUMA == 1) #if (CONFIG_GFXUMA == 1)
msr_t msr, msr2; msr_t msr, msr2;
uint32_t sys_mem; uint32_t sys_mem;
@ -110,6 +111,6 @@ int add_mainboard_resources(struct lb_memory *mem)
return 0; return 0;
} }
struct chip_operations mainboard_ops = { struct chip_operations mainboard_ops = {
CHIP_NAME("AMD PERSIMMON Mainboard") CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER " Mainboard")
.enable_dev = persimmon_enable, .enable_dev = persimmon_enable,
}; };

2
src/northbridge/amd/agesa_wrapper/family14/northbridge.c
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@ -849,7 +849,7 @@ static struct device_operations cpu_bus_ops = {
.set_resources = cpu_bus_set_resources, .set_resources = cpu_bus_set_resources,
.enable_resources = NULL, .enable_resources = NULL,
.init = cpu_bus_init, .init = cpu_bus_init,
.scan_bus = 0, .scan_bus = NULL,
}; };