mb/google/{rex, ovis}: Introduce devicetree.cb for pre-prod SoC
This patch introduces a dedicated devicetree.cb file for platforms built with pre-production SoC. This will help to keep the SoC configuration separate for platforms with ESx and QSx silicons. For example, the SaGv WP configuration is different between pre-production (aka ESx) and production (aka QSx) silicon. BUG=b:306267652 TEST=Able to build and boot google/rex4es. Change-Id: I01b0abeeb25ce5a83882c56b30929228fcc6c95c Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78659 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Mike Lee <mike5@huaqin.corp-partner.google.com>
This commit is contained in:
Subrata Banik
parent
830b0ac4e1
commit
8c4674ee37
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@ -163,6 +163,7 @@ config CHROMEOS_WIFI_SAR
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select USE_SAR
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config DEVICETREE
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default "variants/baseboard/\$(CONFIG_BASEBOARD_DIR)/devicetree_pre_prod.cb" if SOC_INTEL_METEORLAKE_PRE_PRODUCTION_SILICON
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default "variants/baseboard/\$(CONFIG_BASEBOARD_DIR)/devicetree.cb"
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config FMDFILE
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@ -53,19 +53,17 @@ chip soc/intel/meteorlake
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register "sagv" = "SAGV_ENABLED"
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register "sagv_freq_mhz" = "{
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[0] = 3200,
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[1] = 6000,
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[2] = 6400,
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[3] = 5600,
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}"
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register "sagv_freq_mhz[0]" = "2133"
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register "sagv_gear[0]" = "4"
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register "sagv_gear" = "{
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[0] = 4,
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[1] = 4,
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[2] = 4,
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[3] = 2,
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}"
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register "sagv_freq_mhz[1]" = "4267"
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register "sagv_gear[1]" = "4"
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register "sagv_freq_mhz[2]" = "6000"
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register "sagv_gear[2]" = "4"
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register "sagv_freq_mhz[3]" = "6400"
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register "sagv_gear[3]" = "4"
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# Set on-board graphics as primary display
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register "skip_ext_gfx_scan" = "1"
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@ -0,0 +1,96 @@
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chip soc/intel/meteorlake
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# GPE configuration
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register "pmc_gpe0_dw0" = "GPP_D"
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register "pmc_gpe0_dw1" = "GPP_E"
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register "pmc_gpe0_dw2" = "GPP_F"
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# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
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register "gen1_dec" = "0x00fc0801"
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register "gen2_dec" = "0x000c0201"
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# EC memory map range is 0x900-0x9ff
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register "gen3_dec" = "0x00fc0901"
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register "usb2_ports[0]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 0
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register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 1
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register "usb2_ports[2]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 2
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register "usb2_ports[3]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 3
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register "usb2_ports[4]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 4
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register "usb2_ports[5]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 5
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register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 6
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register "usb2_ports[7]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 7
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register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 8
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register "usb2_ports[9]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 9
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register "usb3_ports[0]" = "USB3_PORT_EMPTY" # Disable USB3.0 Port 0
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register "usb3_ports[1]" = "USB3_PORT_EMPTY" # Disable USB3.0 Port 1
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register "tcss_ports[0]" = "TCSS_PORT_EMPTY" # Disable USB-C Port 0
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register "tcss_ports[1]" = "TCSS_PORT_EMPTY" # Disable USB-C Port 1
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register "tcss_ports[2]" = "TCSS_PORT_EMPTY" # Disable USB-C Port 2
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register "tcss_ports[3]" = "TCSS_PORT_EMPTY" # Disable USB-C Port 3
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# S0ix enable
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register "s0ix_enable" = "1"
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# Disable C1 C-state auto-demotion
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register "disable_c1_state_auto_demotion" = "1"
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# Disable PKGC-state demotion
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register "disable_package_c_state_demotion" = "1"
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# Enable Energy Reporting
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register "pch_pm_energy_report_enable" = "1"
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# DPTF enable
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register "dptf_enable" = "1"
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# Temporary setting TCC of 100C = Tj max (110) - TCC_Offset (10)
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register "tcc_offset" = "10"
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# Enable CNVi BT
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register "cnvi_bt_core" = "true"
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register "sagv" = "SAGV_ENABLED"
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register "sagv_freq_mhz[0]" = "3200"
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register "sagv_gear[0]" = "4"
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register "sagv_freq_mhz[1]" = "6000"
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register "sagv_gear[1]" = "4"
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register "sagv_freq_mhz[2]" = "6400"
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register "sagv_gear[2]" = "4"
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register "sagv_freq_mhz[3]" = "5600"
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register "sagv_gear[3]" = "2"
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# Set on-board graphics as primary display
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register "skip_ext_gfx_scan" = "1"
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register "serial_io_uart_mode" = "{
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[PchSerialIoIndexUART0] = PchSerialIoPci,
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[PchSerialIoIndexUART1] = PchSerialIoDisabled,
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[PchSerialIoIndexUART2] = PchSerialIoDisabled,
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}"
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register "pch_hda_dsp_enable" = "1"
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register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T"
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register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"
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register "pch_hda_idisp_codec_enable" = "1"
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device domain 0 on
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device ref igpu on end
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device ref dtt on end
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device ref ioe_shared_sram on end
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device ref xhci on end
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device ref pmc_shared_sram on end
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device ref heci1 on end
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device ref uart0 on end
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device ref soc_espi on
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chip ec/google/chromeec
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device pnp 0c09.0 on end
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end
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end
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end
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end
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@ -0,0 +1,104 @@
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chip soc/intel/meteorlake
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# GPE configuration
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register "pmc_gpe0_dw0" = "GPP_B"
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register "pmc_gpe0_dw1" = "GPP_E"
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register "pmc_gpe0_dw2" = "GPP_F"
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# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
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register "gen1_dec" = "0x00fc0801"
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register "gen2_dec" = "0x000c0201"
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# EC memory map range is 0x900-0x9ff
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register "gen3_dec" = "0x00fc0901"
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register "usb2_ports[0]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 0
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register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 1
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register "usb2_ports[2]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 2
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register "usb2_ports[3]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 3
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register "usb2_ports[4]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 4
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register "usb2_ports[5]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 5
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register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 6
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register "usb2_ports[7]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 7
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register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 8
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register "usb2_ports[9]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 9
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register "usb3_ports[0]" = "USB3_PORT_EMPTY" # Disable USB3.0 Port 0
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register "usb3_ports[1]" = "USB3_PORT_EMPTY" # Disable USB3.0 Port 1
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register "tcss_ports[0]" = "TCSS_PORT_EMPTY" # Disable USB-C Port 0
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register "tcss_ports[1]" = "TCSS_PORT_EMPTY" # Disable USB-C Port 1
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register "tcss_ports[2]" = "TCSS_PORT_EMPTY" # Disable USB-C Port 2
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register "tcss_ports[3]" = "TCSS_PORT_EMPTY" # Disable USB-C Port 3
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# S0ix enable
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register "s0ix_enable" = "1"
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# Disable C1 C-state auto-demotion
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register "disable_c1_state_auto_demotion" = "1"
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# Disable PKGC-state demotion
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register "disable_package_c_state_demotion" = "1"
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# Enable Energy Reporting
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register "pch_pm_energy_report_enable" = "1"
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# DPTF enable
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register "dptf_enable" = "1"
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# Enable CNVi BT
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register "cnvi_bt_core" = "true"
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register "sagv" = "SAGV_ENABLED"
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register "sagv_freq_mhz[0]" = "3200"
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register "sagv_gear[0]" = "4"
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register "sagv_freq_mhz[1]" = "6000"
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register "sagv_gear[1]" = "4"
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register "sagv_freq_mhz[2]" = "6400"
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register "sagv_gear[2]" = "4"
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register "sagv_freq_mhz[3]" = "5600"
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register "sagv_gear[3]" = "2"
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# Set on-board graphics as primary display
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register "skip_ext_gfx_scan" = "1"
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register "serial_io_uart_mode" = "{
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[PchSerialIoIndexUART0] = PchSerialIoPci,
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[PchSerialIoIndexUART1] = PchSerialIoDisabled,
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[PchSerialIoIndexUART2] = PchSerialIoDisabled,
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}"
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register "pch_hda_dsp_enable" = "1"
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register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T"
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register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"
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register "pch_hda_idisp_codec_enable" = "1"
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# As per doc 640982, Intel MTL-U 15W CPU supports FVM on IA and SA
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# The ICC Limit is represented in 1/4 A increments, i.e., a value of 400 = 100A
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# For IA VR configuration
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register "enable_fast_vmode[VR_DOMAIN_IA]" = "1"
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register "cep_enable[VR_DOMAIN_IA]" = "1"
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register "fast_vmode_i_trip[VR_DOMAIN_IA]" = "264" # 66A
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# For SA VR configuration
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register "enable_fast_vmode[VR_DOMAIN_SA]" = "1"
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register "cep_enable[VR_DOMAIN_SA]" = "1"
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register "fast_vmode_i_trip[VR_DOMAIN_SA]" = "84" # 21A
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device domain 0 on
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device ref igpu on end
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device ref dtt on end
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device ref ioe_shared_sram on end
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device ref xhci on end
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device ref pmc_shared_sram on end
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device ref heci1 on end
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device ref uart0 on end
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device ref soc_espi on
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chip ec/google/chromeec
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device pnp 0c09.0 on end
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end
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end
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end
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end
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