Update documentation in smmrelocate.S to mention TSEG
Change-Id: I392f5fc475b15b458fc015e176e45888e7de27fb Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/861 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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@ -54,13 +54,22 @@
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.code16
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/**
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* This trampoline code relocates SMBASE to 0xa0000 - ( lapicid * 0x400 )
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* When starting up, x86 CPUs have their SMBASE set to 0x30000. However,
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* this is not a good place for the SMM handler to live, so it needs to
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* be relocated.
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* Traditionally SMM handlers used to live in the A segment (0xa0000).
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* With growing SMM handlers, more CPU cores, etc. CPU vendors started
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* allowing to relocate the handler to the end of physical memory, which
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* they refer to as TSEG.
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* This trampoline code relocates SMBASE to base address - ( lapicid * 0x400 )
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*
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* Why 0x400? It is a safe value to cover the save state area per CPU. On
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* current AMD CPUs this area is _documented_ to be 0x200 bytes. On Intel
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* Core 2 CPUs the _documented_ parts of the save state area is 48 bytes
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* bigger, effectively sizing our data structures 0x300 bytes.
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*
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* Example (with SMM handler living at 0xa0000):
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*
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* LAPICID SMBASE SMM Entry SAVE STATE
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* 0 0xa0000 0xa8000 0xafd00
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* 1 0x9fc00 0xa7c00 0xaf900
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@ -88,13 +97,7 @@
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* at 0xa8000-0xa8100 (example for core 0). That is not enough.
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*
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* This means we're basically limited to 16 cpu cores before
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* we need to use the TSEG/HSEG for the actual SMM handler plus stack.
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* When we exceed 32 cores, we also need to put SMBASE to TSEG/HSEG.
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*
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* If we figure out the documented values above are safe to use,
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* we could pack the structure above even more, so we could use the
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* scheme to pack save state areas for 63 AMD CPUs or 58 Intel CPUs
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* in the ASEG.
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* we need to move the SMM handler to TSEG.
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*
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* Note: Some versions of Pentium M need their SMBASE aligned to 32k.
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* On those the above only works for up to 2 cores. But for now we only
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