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superio/winbond: remove LDN-specific ops overrides 

The pnp ops struct is already passed to the pnp_enable_devices function and it
is used if no override is supplied in the elements of the pnp_info struct array

Change-Id: I4311834f3970bd3471f2f5a73ca7da3c03936d37
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/27385
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
This commit is contained in:
Felix Held 2018-07-06 20:22:08 +02:00
parent a2c49b0299
commit 8c85880236
9 changed files with 127 additions and 114 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

31
src/superio/winbond/w83627dhg/superio.c
View File

@ -58,21 +58,22 @@ static struct device_operations ops = {
};
static struct pnp_info pnp_dev_info[] = {
{ &ops, W83627DHG_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
{ &ops, W83627DHG_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
{ &ops, W83627DHG_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, W83627DHG_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, W83627DHG_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, 0x07ff, 0x07ff, },
{ &ops, W83627DHG_SPI, PNP_IO1, 0, 0x7f8, },
{ &ops, W83627DHG_GPIO6, },
{ &ops, W83627DHG_WDTO_PLED, },
{ &ops, W83627DHG_GPIO2, },
{ &ops, W83627DHG_GPIO3, },
{ &ops, W83627DHG_GPIO4, },
{ &ops, W83627DHG_GPIO5, },
{ &ops, W83627DHG_ACPI, PNP_IRQ0, },
{ &ops, W83627DHG_HWM, PNP_IO0 | PNP_IRQ0, 0x07fe, },
{ &ops, W83627DHG_PECI_SST, },
{ NULL, W83627DHG_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
{ NULL, W83627DHG_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
{ NULL, W83627DHG_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ NULL, W83627DHG_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ NULL, W83627DHG_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1,
0x07ff, 0x07ff, },
{ NULL, W83627DHG_SPI, PNP_IO1, 0, 0x7f8, },
{ NULL, W83627DHG_GPIO6, },
{ NULL, W83627DHG_WDTO_PLED, },
{ NULL, W83627DHG_GPIO2, },
{ NULL, W83627DHG_GPIO3, },
{ NULL, W83627DHG_GPIO4, },
{ NULL, W83627DHG_GPIO5, },
{ NULL, W83627DHG_ACPI, PNP_IRQ0, },
{ NULL, W83627DHG_HWM, PNP_IO0 | PNP_IRQ0, 0x07fe, },
{ NULL, W83627DHG_PECI_SST, },
};
static void enable_dev(struct device *dev)

35
src/superio/winbond/w83627ehg/superio.c
View File

@ -122,24 +122,25 @@ static struct device_operations ops = {
};
static struct pnp_info pnp_dev_info[] = {
{ &ops, W83627EHG_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
{ &ops, W83627EHG_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
{ &ops, W83627EHG_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, W83627EHG_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, W83627EHG_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, 0x07ff, 0x07ff, },
{ &ops, W83627EHG_SFI, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, W83627EHG_WDTO_PLED, },
{ &ops, W83627EHG_ACPI, PNP_IRQ0, },
{ &ops, W83627EHG_HWM, PNP_IO0 | PNP_IRQ0, 0x07fe, },
{ NULL, W83627EHG_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
{ NULL, W83627EHG_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
{ NULL, W83627EHG_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ NULL, W83627EHG_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ NULL, W83627EHG_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1,
0x07ff, 0x07ff, },
{ NULL, W83627EHG_SFI, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ NULL, W83627EHG_WDTO_PLED, },
{ NULL, W83627EHG_ACPI, PNP_IRQ0, },
{ NULL, W83627EHG_HWM, PNP_IO0 | PNP_IRQ0, 0x07fe, },
{ &ops, W83627EHG_GAME, PNP_IO0, 0x07ff, },
{ &ops, W83627EHG_MIDI, PNP_IO1 | PNP_IRQ0, 0, 0x07fe, },
{ &ops, W83627EHG_GPIO1, },
{ &ops, W83627EHG_GPIO2, },
{ &ops, W83627EHG_GPIO3, },
{ &ops, W83627EHG_GPIO4, },
{ &ops, W83627EHG_GPIO5, },
{ &ops, W83627EHG_GPIO6, },
{ NULL, W83627EHG_GAME, PNP_IO0, 0x07ff, },
{ NULL, W83627EHG_MIDI, PNP_IO1 | PNP_IRQ0, 0, 0x07fe, },
{ NULL, W83627EHG_GPIO1, },
{ NULL, W83627EHG_GPIO2, },
{ NULL, W83627EHG_GPIO3, },
{ NULL, W83627EHG_GPIO4, },
{ NULL, W83627EHG_GPIO5, },
{ NULL, W83627EHG_GPIO6, },
};
static void enable_dev(struct device *dev)

24
src/superio/winbond/w83627hf/superio.c
View File

@ -129,17 +129,19 @@ static struct device_operations ops = {
};
static struct pnp_info pnp_dev_info[] = {
{ &ops, W83627HF_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
{ &ops, W83627HF_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
{ &ops, W83627HF_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, W83627HF_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, W83627HF_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, 0x07ff, 0x07ff, },
{ &ops, W83627HF_CIR, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, W83627HF_GAME_MIDI_GPIO1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07ff, 0x07fe, },
{ &ops, W83627HF_GPIO2, },
{ &ops, W83627HF_GPIO3, },
{ &ops, W83627HF_ACPI, },
{ &ops, W83627HF_HWM, PNP_IO0 | PNP_IRQ0, 0x0ff8, },
{ NULL, W83627HF_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
{ NULL, W83627HF_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
{ NULL, W83627HF_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ NULL, W83627HF_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ NULL, W83627HF_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1,
0x07ff, 0x07ff, },
{ NULL, W83627HF_CIR, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ NULL, W83627HF_GAME_MIDI_GPIO1, PNP_IO0 | PNP_IO1 | PNP_IRQ0,
0x07ff, 0x07fe, },
{ NULL, W83627HF_GPIO2, },
{ NULL, W83627HF_GPIO3, },
{ NULL, W83627HF_ACPI, },
{ NULL, W83627HF_HWM, PNP_IO0 | PNP_IRQ0, 0x0ff8, },
};
static void enable_dev(struct device *dev)

23
src/superio/winbond/w83627thg/superio.c
View File

@ -48,16 +48,19 @@ static struct device_operations ops = {
};
static struct pnp_info pnp_dev_info[] = {
{ &ops, W83627THG_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
{ &ops, W83627THG_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
{ &ops, W83627THG_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, W83627THG_SP2, PNP_IO0 | PNP_IRQ0 | PNP_MSC1, 0x07f8, },
{ &ops, W83627THG_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1 | PNP_MSC0, 0x07ff, 0x07ff, },
{ &ops, W83627THG_GAME_MIDI_GPIO1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07ff, 0x07fe, },
{ &ops, W83627THG_GPIO2, },
{ &ops, W83627THG_GPIO3, PNP_EN | PNP_MSC0 | PNP_MSC1, },
{ &ops, W83627THG_ACPI, PNP_IRQ0, },
{ &ops, W83627THG_HWM, PNP_IO0 | PNP_IRQ0, 0x0ff8, },
{ NULL, W83627THG_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
{ NULL, W83627THG_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
{ NULL, W83627THG_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ NULL, W83627THG_SP2, PNP_IO0 | PNP_IRQ0 | PNP_MSC1, 0x07f8, },
{ NULL, W83627THG_KBC,
PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1 | PNP_MSC0,
0x07ff, 0x07ff, },
{ NULL, W83627THG_GAME_MIDI_GPIO1, PNP_IO0 | PNP_IO1 | PNP_IRQ0,
0x07ff, 0x07fe, },
{ NULL, W83627THG_GPIO2, },
{ NULL, W83627THG_GPIO3, PNP_EN | PNP_MSC0 | PNP_MSC1, },
{ NULL, W83627THG_ACPI, PNP_IRQ0, },
{ NULL, W83627THG_HWM, PNP_IO0 | PNP_IRQ0, 0x0ff8, },
};
static void enable_dev(struct device *dev)

31
src/superio/winbond/w83627uhg/superio.c
View File

@ -94,21 +94,22 @@ static struct device_operations ops = {
};
static struct pnp_info pnp_dev_info[] = {
{ &ops, W83627UHG_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
{ &ops, W83627UHG_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
{ &ops, W83627UHG_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, W83627UHG_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, W83627UHG_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, 0x07ff, 0x07ff, },
{ &ops, W83627UHG_SP3, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, W83627UHG_GPIO3_4, },
{ &ops, W83627UHG_WDTO_PLED_GPIO5_6, },
{ &ops, W83627UHG_GPIO1_2, },
{ &ops, W83627UHG_ACPI, PNP_IRQ0, },
{ &ops, W83627UHG_HWM, PNP_IO0 | PNP_IRQ0, 0x0ff8, },
{ &ops, W83627UHG_PECI_SST, },
{ &ops, W83627UHG_SP4, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, W83627UHG_SP5, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, W83627UHG_SP6, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ NULL, W83627UHG_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
{ NULL, W83627UHG_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
{ NULL, W83627UHG_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ NULL, W83627UHG_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ NULL, W83627UHG_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1,
0x07ff, 0x07ff, },
{ NULL, W83627UHG_SP3, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ NULL, W83627UHG_GPIO3_4, },
{ NULL, W83627UHG_WDTO_PLED_GPIO5_6, },
{ NULL, W83627UHG_GPIO1_2, },
{ NULL, W83627UHG_ACPI, PNP_IRQ0, },
{ NULL, W83627UHG_HWM, PNP_IO0 | PNP_IRQ0, 0x0ff8, },
{ NULL, W83627UHG_PECI_SST, },
{ NULL, W83627UHG_SP4, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ NULL, W83627UHG_SP5, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ NULL, W83627UHG_SP6, PNP_IO0 | PNP_IRQ0, 0x07f8, },
};
static void enable_dev(struct device *dev)

43
src/superio/winbond/w83667hg-a/superio.c
View File

@ -95,27 +95,28 @@ static struct device_operations ops = {
};
static struct pnp_info pnp_dev_info[] = {
{ &ops, W83667HG_A_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x0ff8, },
{ &ops, W83667HG_A_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x0ff8, },
{ &ops, W83667HG_A_SP1, PNP_IO0 | PNP_IRQ0, 0x0ff8, },
{ &ops, W83667HG_A_SP2, PNP_IO0 | PNP_IRQ0, 0x0ff8, },
{ &ops, W83667HG_A_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, 0x0fff, 0x0fff, },
{ &ops, W83667HG_A_SPI1, PNP_IO1, 0, 0x0ff8},
{ &ops, W83667HG_A_WDT1},
{ &ops, W83667HG_A_ACPI},
{ &ops, W83667HG_A_HWM_TSI, PNP_IO0 | PNP_IRQ0, 0x0ffe, },
{ &ops, W83667HG_A_PECI},
{ &ops, W83667HG_A_VID_BUSSEL},
{ &ops, W83667HG_A_GPIO_PP_OD},
{ &ops, W83667HG_A_GPIO1},
{ &ops, W83667HG_A_GPIO2},
{ &ops, W83667HG_A_GPIO3},
{ &ops, W83667HG_A_GPIO4},
{ &ops, W83667HG_A_GPIO5},
{ &ops, W83667HG_A_GPIO6},
{ &ops, W83667HG_A_GPIO7},
{ &ops, W83667HG_A_GPIO8},
{ &ops, W83667HG_A_GPIO9},
{ NULL, W83667HG_A_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x0ff8, },
{ NULL, W83667HG_A_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x0ff8, },
{ NULL, W83667HG_A_SP1, PNP_IO0 | PNP_IRQ0, 0x0ff8, },
{ NULL, W83667HG_A_SP2, PNP_IO0 | PNP_IRQ0, 0x0ff8, },
{ NULL, W83667HG_A_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1,
0x0fff, 0x0fff, },
{ NULL, W83667HG_A_SPI1, PNP_IO1, 0, 0x0ff8},
{ NULL, W83667HG_A_WDT1},
{ NULL, W83667HG_A_ACPI},
{ NULL, W83667HG_A_HWM_TSI, PNP_IO0 | PNP_IRQ0, 0x0ffe, },
{ NULL, W83667HG_A_PECI},
{ NULL, W83667HG_A_VID_BUSSEL},
{ NULL, W83667HG_A_GPIO_PP_OD},
{ NULL, W83667HG_A_GPIO1},
{ NULL, W83667HG_A_GPIO2},
{ NULL, W83667HG_A_GPIO3},
{ NULL, W83667HG_A_GPIO4},
{ NULL, W83667HG_A_GPIO5},
{ NULL, W83667HG_A_GPIO6},
{ NULL, W83667HG_A_GPIO7},
{ NULL, W83667HG_A_GPIO8},
{ NULL, W83667HG_A_GPIO9},
};
static void enable_dev(struct device *dev)

21
src/superio/winbond/w83697hf/superio.c
View File

@ -77,16 +77,17 @@ static struct device_operations ops = {
};
static struct pnp_info pnp_dev_info[] = {
{ &ops, W83697HF_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
{ &ops, W83697HF_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
{ &ops, W83697HF_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, W83697HF_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, W83697HF_CIR, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, W83697HF_GAME_GPIO1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07ff, 0x07fe, },
{ &ops, W83697HF_MIDI_GPIO5, },
{ &ops, W83697HF_GPIO234, },
{ &ops, W83697HF_ACPI, },
{ &ops, W83697HF_HWM, PNP_IO0 | PNP_IRQ0, 0x0ff8, },
{ NULL, W83697HF_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
{ NULL, W83697HF_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
{ NULL, W83697HF_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ NULL, W83697HF_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ NULL, W83697HF_CIR, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ NULL, W83697HF_GAME_GPIO1, PNP_IO0 | PNP_IO1 | PNP_IRQ0,
0x07ff, 0x07fe, },
{ NULL, W83697HF_MIDI_GPIO5, },
{ NULL, W83697HF_GPIO234, },
{ NULL, W83697HF_ACPI, },
{ NULL, W83697HF_HWM, PNP_IO0 | PNP_IRQ0, 0x0ff8, },
};
static void enable_dev(struct device *dev)

18
src/superio/winbond/w83977tf/superio.c
View File

@ -49,14 +49,16 @@ static struct device_operations ops = {
};
static struct pnp_info pnp_dev_info[] = {
{ &ops, W83977TF_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
{ &ops, W83977TF_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
{ &ops, W83977TF_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, W83977TF_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, W83977TF_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, 0x07ff, 0x07ff, },
{ &ops, W83977TF_CIR, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, W83977TF_GAME_MIDI_GPIO1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07ff, 0x07fe, },
{ &ops, W83977TF_ACPI, PNP_IRQ0, },
{ NULL, W83977TF_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
{ NULL, W83977TF_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
{ NULL, W83977TF_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ NULL, W83977TF_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ NULL, W83977TF_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1,
0x07ff, 0x07ff, },
{ NULL, W83977TF_CIR, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ NULL, W83977TF_GAME_MIDI_GPIO1, PNP_IO0 | PNP_IO1 | PNP_IRQ0,
0x07ff, 0x07fe, },
{ NULL, W83977TF_ACPI, PNP_IRQ0, },
};
static void enable_dev(struct device *dev)

15
src/superio/winbond/wpcd376i/superio.c
View File

@ -55,13 +55,14 @@ static struct device_operations ops = {
};
static struct pnp_info pnp_dev_info[] = {
{ &ops, WPCD376I_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07fa, },
{ &ops, WPCD376I_LPT, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x04f8, },
{ &ops, WPCD376I_IR, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, 0x07f8, },
{ &ops, WPCD376I_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, WPCD376I_KBCM, PNP_IRQ0, },
{ &ops, WPCD376I_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07f8, 0x07f8, },
{ &ops, WPCD376I_GPIO, PNP_IO0 | PNP_IRQ0, 0xfff8, },
{ NULL, WPCD376I_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07fa, },
{ NULL, WPCD376I_LPT, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x04f8, },
{ NULL, WPCD376I_IR, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1,
0x07f8, },
{ NULL, WPCD376I_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ NULL, WPCD376I_KBCM, PNP_IRQ0, },
{ NULL, WPCD376I_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07f8, 0x07f8, },
{ NULL, WPCD376I_GPIO, PNP_IO0 | PNP_IRQ0, 0xfff8, },
};
static void enable_dev(struct device *dev)