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Intel Panther Point PCH: Use 2 << 24 to clarify that APIC ID is 2 

Commit »Add support for Intel Panther Point PCH« (8e073829) [1] used
`1 << 25` to set the APIC ID of 2. Using `2 << 24`, which is the same
value, instead makes it clear, that the APIC ID is 2.

[1] http://review.coreboot.org/853

Change-Id: I5044dc470120cde2d2cdfc6e9ead17ddb47b6453
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3100
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
This commit is contained in:
Vladimir Serbinenko 2013-03-12 15:53:44 +01:00 committed by Marc Jones
parent 8a2bc62d4c
commit 8c937c7e3c
1 changed files with 2 additions and 2 deletions
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4
src/southbridge/intel/bd82x6x/lpc.c
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@ -52,7 +52,7 @@ static void pch_enable_apic(struct device *dev)
pci_write_config8(dev, ACPI_CNTL, 0x80); pci_write_config8(dev, ACPI_CNTL, 0x80);
*ioapic_index = 0; *ioapic_index = 0;
*ioapic_data = (1 << 25); *ioapic_data = (2 << 24);
/* affirm full set of redirection table entries ("write once") */ /* affirm full set of redirection table entries ("write once") */
*ioapic_index = 1; *ioapic_index = 1;
@ -63,7 +63,7 @@ static void pch_enable_apic(struct device *dev)
*ioapic_index = 0; *ioapic_index = 0;
reg32 = *ioapic_data; reg32 = *ioapic_data;
printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", (reg32 >> 24) & 0x0f); printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", (reg32 >> 24) & 0x0f);
if (reg32 != (1 << 25)) if (reg32 != (2 << 24))
die("APIC Error\n"); die("APIC Error\n");
printk(BIOS_SPEW, "Dumping IOAPIC registers\n"); printk(BIOS_SPEW, "Dumping IOAPIC registers\n");