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soc/intel/common: Define post codes 

For the most part, this just moves the existing post codes into macros
so that they're not just bare numbers.

cache_as_ram.S:
Post code 0x28 was previously pointless with just a single jump between
it and post code 0x29, car_init_done.  This code was removed, and the
0x28 value was used to differentiate the car_nem_enhanced subroutine
from the other 0x26 post codes used before calling the clear_car
subroutine.

All other post codes remain identical.

POST_BOOTBLOCK and POST_CODE_ZERO are expected to become global, whereas
the POST_SOC codes are expected to be Intel only.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I82a34960ae73fc263359e4519234ee78e7e3daab
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69865
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Martin Roth 2022-11-20 17:56:44 -07:00 committed by Martin L Roth
parent d05ea79e40
commit 8c974509ea
4 changed files with 43 additions and 22 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

35
src/soc/intel/common/block/cpu/car/cache_as_ram.S
View File

@ -8,6 +8,7 @@
#include <cpu/x86/mtrr.h>
#include <cpu/x86/post_code.h>
#include <intelblocks/msr.h>
#include <intelblocks/post_codes.h>
.section .init, "ax", @progbits
@ -77,7 +78,7 @@
.global bootblock_pre_c_entry
bootblock_pre_c_entry:
post_code(0x20)
post_code(POST_BOOTBLOCK_PRE_C_ENTRY)
/* Bootguard sets up its own CAR and needs separate handling */
check_boot_guard:
@ -97,7 +98,7 @@ no_bootguard:
jmp check_mtrr /* Check if CPU properly reset */
no_reset:
post_code(0x21)
post_code(POST_SOC_NO_RESET)
/* Clear/disable fixed MTRRs */
mov $fixed_mtrr_list_size, %ebx
@ -110,7 +111,7 @@ clear_fixed_mtrr:
wrmsr
jnz clear_fixed_mtrr
post_code(0x22)
post_code(POST_SOC_CLEAR_FIXED_MTRRS)
/* Figure out how many MTRRs we have, and clear them out */
mov $MTRR_CAP_MSR, %ecx
@ -128,7 +129,7 @@ clear_var_mtrr:
dec %ebx
jnz clear_var_mtrr
post_code(0x23)
post_code(POST_SOC_CLEAR_VAR_MTRRS)
/* Configure default memory type to uncacheable (UC) */
mov $MTRR_DEF_TYPE_MSR, %ecx
@ -156,7 +157,7 @@ setup_car_mtrr:
bts %eax, %esi
dec %esi /* esi <- MTRR_PHYS_MASK_HIGH */
post_code(0x24)
post_code(POST_SOC_SET_UP_CAR_MTRRS)
#if ((CONFIG_DCACHE_RAM_SIZE & (CONFIG_DCACHE_RAM_SIZE - 1)) == 0)
find_free_mtrr
@ -215,7 +216,7 @@ setup_car_mtrr:
#else
#error "DCACHE_RAM_SIZE is not a power of 2 and setup code is missing"
#endif
post_code(0x25)
post_code(POST_SOC_BOOTGUARD_SETUP)
is_bootguard_nem
jz no_bootguard_car_continue
@ -267,7 +268,7 @@ no_bootguard_car_continue:
.global car_init_done
car_init_done:
post_code(0x29)
post_code(POST_SOC_CAR_INIT_DONE)
/* Setup bootblock stack */
mov $_ecar_stack, %esp
@ -294,7 +295,7 @@ car_init_done:
#endif
before_carstage:
post_code(0x2a)
post_code(POST_SOC_BEFORE_CARSTAGE)
call bootblock_c_entry
/* Never reached */
@ -327,11 +328,11 @@ car_nem:
or $0x1, %eax
wrmsr
post_code(0x26)
post_code(POST_SOC_CLEARING_CAR)
clear_car
post_code(0x27)
post_code(POST_SOC_DISABLE_CACHE_EVICT)
/* Disable cache eviction (run stage) */
mov $MSR_EVICT_CTL, %ecx
@ -339,8 +340,6 @@ car_nem:
or $0x2, %eax
wrmsr
post_code(0x28)
jmp car_init_done
#elif CONFIG(INTEL_CAR_CQOS)
@ -418,11 +417,11 @@ car_cqos:
and %ebx, %eax
wrmsr
post_code(0x26)
post_code(POST_SOC_CLEARING_CAR)
clear_car
post_code(0x27)
post_code(POST_SOC_DISABLE_CACHE_EVICT)
/* Cache is populated. Use mask 1 that will block evicts */
mov $IA32_PQR_ASSOC, %ecx
@ -437,8 +436,6 @@ car_cqos:
and $~(PREFETCH_L1_DISABLE | PREFETCH_L2_DISABLE), %eax
wrmsr
post_code(0x28)
jmp car_init_done
#elif CONFIG(INTEL_CAR_NEM_ENHANCED)
@ -449,7 +446,7 @@ car_nem_enhanced:
rdmsr
or $0x1, %eax
wrmsr
post_code(0x26)
post_code(POST_SOC_CAR_NEM_ENHANCED)
/* Create n-way set associativity of cache */
xorl %edi, %edi
@ -636,7 +633,7 @@ program_sf2:
#endif
wrmsr
post_code(0x27)
post_code(POST_SOC_DISABLE_CACHE_EVICT)
/*
* Enable No-Eviction Mode Run State by setting
* NO_EVICT_MODE MSR 2E0h bit [1] = '1'.
@ -647,7 +644,5 @@ program_sf2:
orl $0x02, %eax
wrmsr
post_code(0x28)
jmp car_init_done
#endif

3
src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S
View File

@ -3,6 +3,7 @@
#include <device/pci_def.h>
#include <cpu/x86/cr.h>
#include <cpu/x86/post_code.h>
#include <intelblocks/post_codes.h>
#define CBFS_FILE_MAGIC 0
#define CBFS_FILE_LEN (CBFS_FILE_MAGIC + 8)
@ -19,7 +20,7 @@ bootblock_pre_c_entry:
.global cache_as_ram
cache_as_ram:
post_code(0x21)
post_code(POST_BOOTBLOCK_CAR)
movl $(CONFIG_FSP_T_LOCATION), %ebx
add $0x94, %ebx

3
src/soc/intel/common/block/cse/cse.c
View File

@ -12,6 +12,7 @@
#include <device/pci_ops.h>
#include <intelblocks/cse.h>
#include <intelblocks/pmclib.h>
#include <intelblocks/post_codes.h>
#include <option.h>
#include <security/vboot/misc.h>
#include <security/vboot/vboot_common.h>
@ -611,7 +612,7 @@ int heci_reset(void)
uint32_t csr;
/* Clear post code to prevent eventlog entry from unknown code. */
post_code(0);
post_code(POST_CODE_ZERO);
/* Send reset request */
csr = read_host_csr();

24
src/soc/intel/common/block/include/intelblocks/post_codes.h Normal file
View File

@ -0,0 +1,24 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef SOC_INTEL_COMMON_BLOCK_POST_CODES_H
#define SOC_INTEL_COMMON_BLOCK_POST_CODES_H
/* common/block/cpu/car/cache_as_ram.s */
#define POST_BOOTBLOCK_PRE_C_ENTRY 0x20
#define POST_SOC_NO_RESET 0x21
#define POST_SOC_CLEAR_FIXED_MTRRS 0x22
#define POST_SOC_CLEAR_VAR_MTRRS 0x23
#define POST_SOC_SET_UP_CAR_MTRRS 0x24
#define POST_SOC_BOOTGUARD_SETUP 0x25
#define POST_SOC_CLEARING_CAR 0x26
#define POST_SOC_DISABLE_CACHE_EVICT 0x27
#define POST_SOC_CAR_NEM_ENHANCED 0x28
#define POST_SOC_CAR_INIT_DONE 0x29
#define POST_SOC_BEFORE_CARSTAGE 0x2a
/* common/block/cpu/car/cache_as_ram_fsp.S */
#define POST_BOOTBLOCK_CAR 0x21
/* common/block/cse/cse.c */
#define POST_CODE_ZERO 0x00
#endif