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arch/x86/ioapic: Drop irq_on_fsb as a configurable item 

APIC Serial Bus pins were removed with ICH5 already, so a choice
'irq_on_fsb = 0' would not take effect. The related register BOOT_CONFIG
0x3 is also not documented since ICH5.

For emulation/qemu-q35 with ICH9 the choice INTERRUPT_ON_APIC_BUS was
wrong and ignored as BOOT_CONFIG register emulation was never implemented.

For ICH4 and earlier, the choice to use FSB can be made based on the
installed CPU model but this is now just hardwired to match P4 CPUs of
aopen/dxplplusu.

For sb/intel/i82371eb register BOOT_CONFIG 0x3 is also not defined
and the only possible operation mode there is APIC Serial Bus, which
requires no configuration.

Change-Id: Id433e0e67cb83b44a3041250481f307b2ed1ad18
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55257
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kyösti Mälkki 2021-06-06 08:14:57 +03:00
parent d614e85418
commit 8c9a89de99
18 changed files with 13 additions and 73 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
src/arch/x86/Kconfig
View File

@ -172,14 +172,6 @@ config CMOS_DEFAULT_FILE
default "src/mainboard/\$(MAINBOARDDIR)/cmos.default"
depends on HAVE_CMOS_DEFAULT
config IOAPIC_INTERRUPTS_ON_FSB
bool
default y if !IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS
config IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS
bool
default n
config HPET_ADDRESS_OVERRIDE
def_bool n

4
src/arch/x86/include/arch/ioapic.h
View File

@ -34,8 +34,8 @@ u8 get_ioapic_version(void *ioapic_base);
void setup_ioapic(void *ioapic_base, u8 ioapic_id);
void clear_ioapic(void *ioapic_base);
void setup_ioapic_helper(void *ioapic_base, u8 ioapic_id, bool irq_on_fsb,
bool enable_virtual_wire);
void ioapic_set_boot_config(void *ioapic_base, bool irq_on_fsb);
void setup_ioapic_helper(void *ioapic_base, u8 ioapic_id, bool enable_virtual_wire);
#endif
#endif

17
src/arch/x86/ioapic.c
View File

@ -119,13 +119,8 @@ u8 get_ioapic_version(void *ioapic_base)
return io_apic_read(ioapic_base, 0x01) & 0xff;
}
void setup_ioapic_helper(void *ioapic_base, u8 ioapic_id, bool irq_on_fsb,
bool enable_virtual_wire)
void ioapic_set_boot_config(void *ioapic_base, bool irq_on_fsb)
{
int first = 0, last;
set_ioapic_id(ioapic_base, ioapic_id);
if (irq_on_fsb) {
/*
* For the Pentium 4 and above APICs deliver their interrupts
@ -139,6 +134,13 @@ void setup_ioapic_helper(void *ioapic_base, u8 ioapic_id, bool irq_on_fsb,
"IOAPIC: Enabling interrupts on APIC serial bus\n");
io_apic_write(ioapic_base, 0x03, 0);
}
}
void setup_ioapic_helper(void *ioapic_base, u8 ioapic_id, bool enable_virtual_wire)
{
int first = 0, last;
set_ioapic_id(ioapic_base, ioapic_id);
if (enable_virtual_wire) {
route_i8259_irq0(ioapic_base);
@ -152,6 +154,5 @@ void setup_ioapic_helper(void *ioapic_base, u8 ioapic_id, bool irq_on_fsb,
void setup_ioapic(void *ioapic_base, u8 ioapic_id)
{
setup_ioapic_helper(ioapic_base, ioapic_id,
CONFIG(IOAPIC_INTERRUPTS_ON_FSB), true);
setup_ioapic_helper(ioapic_base, ioapic_id, true);
}

1
src/drivers/generic/ioapic/chip.h
View File

@ -6,7 +6,6 @@
typedef struct drivers_generic_ioapic_config {
u32 version;
u8 apicid;
u8 irq_on_fsb;
u8 enable_virtual_wire;
u8 have_isa_interrupts;
void *base;

3
src/drivers/generic/ioapic/ioapic.c
View File

@ -13,8 +13,7 @@ static void ioapic_init(struct device *dev)
if (!dev->enabled || !config)
return;
setup_ioapic_helper(config->base, config->apicid, config->irq_on_fsb,
config->enable_virtual_wire);
setup_ioapic_helper(config->base, config->apicid, config->enable_virtual_wire);
}
static void ioapic_read_resources(struct device *dev)

1
src/mainboard/emulation/qemu-q35/Kconfig
View File

@ -4,7 +4,6 @@ config BOARD_SPECIFIC_OPTIONS
def_bool y
select CPU_QEMU_X86
select SOUTHBRIDGE_INTEL_I82801IX
select IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS
select HAVE_CMOS_DEFAULT
select HAVE_OPTION_TABLE
# select HAVE_PIRQ_TABLE

1
src/mainboard/lenovo/t400/devicetree.cb
View File

@ -143,7 +143,6 @@ chip northbridge/intel/gm45
chip drivers/generic/ioapic
register "have_isa_interrupts" = "1"
register "irq_on_fsb" = "1"
register "enable_virtual_wire" = "1"
register "base" = "(void *)0xfec00000"
device ioapic 2 on end

1
src/mainboard/lenovo/x200/devicetree.cb
View File

@ -133,7 +133,6 @@ chip northbridge/intel/gm45
chip drivers/generic/ioapic
register "have_isa_interrupts" = "1"
register "irq_on_fsb" = "1"
register "enable_virtual_wire" = "1"
register "base" = "(void *)0xfec00000"
device ioapic 2 on end

1
src/mainboard/roda/rk9/devicetree.cb
View File

@ -121,7 +121,6 @@ chip northbridge/intel/gm45
device pci 1f.0 on # LPC bridge
chip drivers/generic/ioapic
register "have_isa_interrupts" = "1"
register "irq_on_fsb" = "1"
register "enable_virtual_wire" = "1"
register "base" = "(void *)0xfec00000"
device ioapic 2 on end

1
src/mainboard/samsung/lumpy/devicetree.cb
View File

@ -107,7 +107,6 @@ chip northbridge/intel/sandybridge
chip drivers/generic/ioapic
register "have_isa_interrupts" = "1"
register "irq_on_fsb" = "1"
register "enable_virtual_wire" = "1"
register "base" = "(void *)0xfec00000"
device ioapic 4 on end

6
src/soc/intel/broadwell/pch/lpc.c
View File

@ -42,12 +42,6 @@ static void pch_enable_ioapic(struct device *dev)
reg32 |= 0x00270000;
io_apic_write(VIO_APIC_VADDR, 0x01, reg32);
/*
* Select Boot Configuration register (0x03) and
* use Processor System Bus (0x01) to deliver interrupts.
*/
io_apic_write(VIO_APIC_VADDR, 0x03, 0x01);
}
static void enable_hpet(struct device *dev)

6
src/soc/intel/common/block/lpc/lpc_lib.c
View File

@ -290,12 +290,6 @@ void pch_enable_ioapic(void)
reg32 |= (redir_entries - 1) << 16;
io_apic_write((void *)IO_APIC_ADDR, 0x01, reg32);
/*
* Select Boot Configuration register (0x03) and
* use Processor System Bus (0x01) to deliver interrupts.
*/
io_apic_write((void *)IO_APIC_ADDR, 0x03, 0x01);
}
static const uint8_t pch_interrupt_routing[PIRQ_COUNT] = {

6
src/soc/intel/denverton_ns/lpc.c
View File

@ -42,12 +42,6 @@ static void pch_enable_ioapic(struct device *dev)
reg32 |= (PCH_LP_REDIR_ETR - 1) << 16;
io_apic_write((void *)IO_APIC_ADDR, 0x01, reg32);
/*
* Select Boot Configuration register (0x03) and
* use Processor System Bus (0x01) to deliver interrupts.
*/
io_apic_write((void *)IO_APIC_ADDR, 0x03, 0x01);
}
/* interrupt router lookup for internal devices */

6
src/southbridge/intel/bd82x6x/lpc.c
View File

@ -48,12 +48,6 @@ static void pch_enable_ioapic(struct device *dev)
/* affirm full set of redirection table entries ("write once") */
reg32 = io_apic_read(VIO_APIC_VADDR, 0x01);
io_apic_write(VIO_APIC_VADDR, 0x01, reg32);
/*
* Select Boot Configuration register (0x03) and
* use Processor System Bus (0x01) to deliver interrupts.
*/
io_apic_write(VIO_APIC_VADDR, 0x03, 0x01);
}
static void pch_enable_serial_irqs(struct device *dev)

6
src/southbridge/intel/i82801dx/lpc.c
View File

@ -50,11 +50,7 @@ static void i82801dx_enable_ioapic(struct device *dev)
set_ioapic_id(VIO_APIC_VADDR, 0x02);
/*
* Select Boot Configuration register (0x03) and
* use Processor System Bus (0x01) to deliver interrupts.
*/
io_apic_write(VIO_APIC_VADDR, 0x03, 0x01);
ioapic_set_boot_config(VIO_APIC_VADDR, true);
}
static void i82801dx_enable_serial_irqs(struct device *dev)

6
src/southbridge/intel/i82801gx/lpc.c
View File

@ -34,12 +34,6 @@
static void i82801gx_enable_ioapic(struct device *dev)
{
set_ioapic_id(VIO_APIC_VADDR, 0x02);
/*
* Select Boot Configuration register (0x03) and
* use Processor System Bus (0x01) to deliver interrupts.
*/
io_apic_write(VIO_APIC_VADDR, 0x03, 0x01);
}
static void i82801gx_enable_serial_irqs(struct device *dev)

6
src/southbridge/intel/ibexpeak/lpc.c
View File

@ -40,12 +40,6 @@ static void pch_enable_ioapic(struct device *dev)
/* affirm full set of redirection table entries ("write once") */
reg32 = io_apic_read(VIO_APIC_VADDR, 0x01);
io_apic_write(VIO_APIC_VADDR, 0x01, reg32);
/*
* Select Boot Configuration register (0x03) and
* use Processor System Bus (0x01) to deliver interrupts.
*/
io_apic_write(VIO_APIC_VADDR, 0x03, 0x01);
}
static void pch_enable_serial_irqs(struct device *dev)

6
src/southbridge/intel/lynxpoint/lpc.c
View File

@ -49,12 +49,6 @@ static void pch_enable_ioapic(struct device *dev)
reg32 |= 0x00270000;
}
io_apic_write(VIO_APIC_VADDR, 0x01, reg32);
/*
* Select Boot Configuration register (0x03) and
* use Processor System Bus (0x01) to deliver interrupts.
*/
io_apic_write(VIO_APIC_VADDR, 0x03, 0x01);
}
static void pch_enable_serial_irqs(struct device *dev)