From 8cab80c84f2be22e1f45a2b31c8019695b70abb2 Mon Sep 17 00:00:00 2001
From: Felix Held <felix-coreboot@felixheld.de>
Date: Fri, 5 May 2023 15:20:15 +0200
Subject: [PATCH] soc/amd/common/acpi: move acpi_fill_root_complex_tom to
 Stoneyridge

Now that Stoneyridge is the only AMD SoC that still needs the part of
the SSDT that contains the TOM1 and TOM2, move it from the common code
to the Stoneyridge northbridge code.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I9091360d6a82183092ef75417ad652523babe075
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75564
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
---
 src/soc/amd/common/block/acpi/tables.c        | 28 -------------------
 .../amd/common/block/include/amdblocks/acpi.h |  2 --
 src/soc/amd/stoneyridge/northbridge.c         | 25 +++++++++++++++++
 3 files changed, 25 insertions(+), 30 deletions(-)

diff --git a/src/soc/amd/common/block/acpi/tables.c b/src/soc/amd/common/block/acpi/tables.c
index aaa851e0ac..bda283a3cb 100644
--- a/src/soc/amd/common/block/acpi/tables.c
+++ b/src/soc/amd/common/block/acpi/tables.c
@@ -3,9 +3,6 @@
 #include <acpi/acpi.h>
 #include <acpi/acpigen.h>
 #include <amdblocks/acpi.h>
-#include <amdblocks/chip.h>
-#include <assert.h>
-#include <cpu/amd/mtrr.h>
 #include <device/device.h>
 #include <types.h>
 
@@ -15,28 +12,3 @@ unsigned long southbridge_write_acpi_tables(const struct device *device,
 {
 	return acpi_write_hpet(device, current, rsdp);
 }
-
-/* Used by \_SB.PCI0._CRS */
-void acpi_fill_root_complex_tom(const struct device *device)
-{
-	const char *scope;
-
-	assert(device);
-
-	scope = acpi_device_scope(device);
-	assert(scope);
-	acpigen_write_scope(scope);
-
-	acpigen_write_name_dword("TOM1", get_top_of_mem_below_4gb());
-
-	/*
-	 * Since XP only implements parts of ACPI 2.0, we can't use a qword
-	 * here.
-	 * See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt
-	 * slide 22ff.
-	 * Shift value right by 20 bit to make it fit into 32bit,
-	 * giving us 1MB granularity and a limit of almost 4Exabyte of memory.
-	 */
-	acpigen_write_name_dword("TOM2", get_top_of_mem_above_4gb() >> 20);
-	acpigen_pop_len();
-}
diff --git a/src/soc/amd/common/block/include/amdblocks/acpi.h b/src/soc/amd/common/block/include/amdblocks/acpi.h
index 91051841f5..682f8ca7fd 100644
--- a/src/soc/amd/common/block/include/amdblocks/acpi.h
+++ b/src/soc/amd/common/block/include/amdblocks/acpi.h
@@ -54,8 +54,6 @@ struct chipset_power_state {
 unsigned long southbridge_write_acpi_tables(const struct device *device, unsigned long current,
 					    struct acpi_rsdp *rsdp);
 
-void acpi_fill_root_complex_tom(const struct device *device);
-
 uintptr_t add_agesa_fsp_acpi_table(guid_t guid, const char *name, acpi_rsdp_t *rsdp,
 				   uintptr_t current);
 
diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c
index 452a7bb2eb..90d227ade0 100644
--- a/src/soc/amd/stoneyridge/northbridge.c
+++ b/src/soc/amd/stoneyridge/northbridge.c
@@ -167,6 +167,31 @@ static void northbridge_init(struct device *dev)
 	register_new_ioapic((u8 *)IO_APIC2_ADDR);
 }
 
+/* Used by \_SB.PCI0._CRS */
+static void acpi_fill_root_complex_tom(const struct device *device)
+{
+	const char *scope;
+
+	assert(device);
+
+	scope = acpi_device_scope(device);
+	assert(scope);
+	acpigen_write_scope(scope);
+
+	acpigen_write_name_dword("TOM1", get_top_of_mem_below_4gb());
+
+	/*
+	 * Since XP only implements parts of ACPI 2.0, we can't use a qword
+	 * here.
+	 * See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt
+	 * slide 22ff.
+	 * Shift value right by 20 bit to make it fit into 32bit,
+	 * giving us 1MB granularity and a limit of almost 4Exabyte of memory.
+	 */
+	acpigen_write_name_dword("TOM2", get_top_of_mem_above_4gb() >> 20);
+	acpigen_pop_len();
+}
+
 static unsigned long acpi_fill_hest(acpi_hest_t *hest)
 {
 	void *addr, *current;