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mb/google/brox: Switch EC INT and WAKE GPIOs 

There was a mistake in the gpio spreadsheet provided by the HW team
and the GPIO assignments for the EC INT and WAKE signals got switched
from what it was in the schematics.  The correct assignments are:
    GPP_D0 = EC_PCH_INT_ODL
    GPP_D1 = EC_PCH_WAKE_ODL

BUG=b:311450057,b:300690448
BRANCH=None
TEST=emerge-brox coreboot
     Will try to boot OS image on device and see if there are any
     ec errors.

Change-Id: I02057aeb5d82218dbbe4c939d4feb87a4d3da678
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79886
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Shelley Chen 2024-01-09 17:05:54 -08:00
parent 972cd627a2
commit 8cae0860e9
2 changed files with 7 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
src/mainboard/google/brox/variants/baseboard/brox/gpio.c
View File

@ -139,10 +139,10 @@ static const struct pad_config gpio_table[] = {
/* GPP_C7 : SML1DATA ==> SOC_I2C_PD_SDA (NC) */
PAD_NC(GPP_C7, NONE),
/* GPP_D0 : [NF1: ISH_GP0 NF2: BK0 NF5: SBK0 NF6: USB_C_GPP_D0] ==> PCH_EC_PCH_WAKE_ODL */
PAD_CFG_GPI_IRQ_WAKE(GPP_D0, NONE, DEEP, EDGE_SINGLE, INVERT),
/* GPP_D1 : [NF1: ISH_GP1 NF2: BK1 NF5: SBK1 NF6: USB_C_GPP_D1] ==> PCH_EC_PCH_INT_ODL */
PAD_CFG_GPI_INT(GPP_D1, NONE, PLTRST, LEVEL),
/* GPP_D0 : [NF1: ISH_GP0 NF2: BK0 NF5: SBK0 NF6: USB_C_GPP_D0] ==> PCH_EC_PCH_INT_ODL */
PAD_CFG_GPI_INT(GPP_D0, NONE, PLTRST, LEVEL),
/* GPP_D1 : [NF1: ISH_GP1 NF2: BK1 NF5: SBK1 NF6: USB_C_GPP_D1] ==> PCH_EC_PCH_WAKE_ODL */
PAD_CFG_GPI_IRQ_WAKE(GPP_D1, NONE, DEEP, EDGE_SINGLE, INVERT),
/* GPP_D2 : [NF1: ISH_GP2 NF2: BK2 NF5: SBK2 NF6: USB_C_GPP_D2] ==> ISH_ACCEL_DB_INT_L (NC) */
PAD_NC(GPP_D2, NONE),
/* GPP_D3 : [NF1: ISH_GP3 NF2: BK3 NF5: SBK3 NF6: USB_C_GPP_D3] ==> ISH_ACCEL_MB_INT_L (NC) */

6
src/mainboard/google/brox/variants/baseboard/brox/include/baseboard/gpio.h
View File

@ -8,13 +8,13 @@
/* eSPI virtual wire reporting */
#define EC_SCI_GPI GPE0_ESPI
/* EC wake is EC_PCH_INT which is routed to GPP_D1 pin */
#define GPE_EC_WAKE GPE0_DW1_01
/* EC wake is EC_PCH_INT which is routed to GPP_D0 pin */
#define GPE_EC_WAKE GPE0_DW1_00
/* WP signal to PCH */
#define GPIO_PCH_WP GPP_E8
/* Used to gate SoC's SLP_S0# signal */
#define GPIO_SLP_S0_GATE GPP_D17
/* GPIO IRQ for tight timestamps / wake support */
#define EC_SYNC_IRQ GPP_D1_IRQ
#define EC_SYNC_IRQ GPP_D0_IRQ
#endif /* __BASEBOARD_GPIO_H__ */