diff --git a/src/arch/i386/lib/cpu.c b/src/arch/i386/lib/cpu.c
index f459f3a853..9af2bfb8c0 100644
--- a/src/arch/i386/lib/cpu.c
+++ b/src/arch/i386/lib/cpu.c
@@ -126,15 +126,15 @@ unsigned long cpu_initialize(struct mem_range *mem)
 	unsigned long processor_id = this_processors_id();
 	printk_notice("Initializing CPU #%d\n", processor_id);
 
-	/* some cpus need a fixup done. This is the hook for doing that. */
-	cpufixup(mem);
-
 	/* Turn on caching if we haven't already */
 	cache_on(mem);
 
 	display_cpuid();
 	mtrr_check();
 
+	/* some cpus need a fixup done. This is the hook for doing that. */
+	cpufixup(mem);
+
 #if 0
 	/* now that everything is really up, enable the l2 cache if desired. 
 	 * The enable can wait until this point, because linuxbios and it's
@@ -142,6 +142,7 @@ unsigned long cpu_initialize(struct mem_range *mem)
 	 */
 	configure_l2_cache();
 #endif
+
 	interrupts_on();
 	processor_id = this_processors_id();
 	printk_info("CPU #%d Initialized\n", processor_id);
diff --git a/src/cpu/k8/cpufixup.c b/src/cpu/k8/cpufixup.c
index c25a473d2e..6edfe73bf6 100644
--- a/src/cpu/k8/cpufixup.c
+++ b/src/cpu/k8/cpufixup.c
@@ -134,10 +134,11 @@ static void set_init_ecc_mtrrs(void)
 {
 	msr_t msr;
 	int i;
+
 	disable_cache();
 
 	/* First clear all of the msrs to be safe */
-	for(i = 0; i < MTRR_COUNT; i++) {
+	for (i = 0; i < MTRR_COUNT; i++) {
 		msr_t zero;
 		zero.lo = zero.hi = 0;
 		wrmsr(MTRRphysBase_MSR(i), zero);
@@ -165,7 +166,6 @@ static void set_init_ecc_mtrrs(void)
 	enable_cache();
 }
 
-
 static void init_ecc_memory(void)
 {
 	unsigned long startk, begink, endk;