baytrail: add lpe codec clock configuration

Add device tree option to determine if the LPE
audio codec has a platform clock signal connected
to it from the SoC. If a frequency is selected the
platform clock number is used to enable the
clock.

BUG=chrome-os-partner:23791
BRANCH=None
TEST=Built and booted rambi with 25MHz option. Probed pin
     to audio codec. Noted 25MHz clock.

Change-Id: I67d0d034f30ae1c7ee8269c0aea43e8c92ff868c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/178780
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/4986
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)

src/soc/intel/baytrail/baytrail/pmc.h

@@ -73,6 +73,17 @@
 #	define ROUTE_NONE	0
 #	define ROUTE_SMI	1
 #	define ROUTE_SCI	2
+#define PLT_CLK_CTL_0	0x60
+#define PLT_CLK_CTL_1	0x64
+#define PLT_CLK_CTL_2	0x68
+#define PLT_CLK_CTL_3	0x6c
+#define PLT_CLK_CTL_4	0x70
+#define PLT_CLK_CTL_5	0x74
+#	define CLK_FREQ_25MHZ	(0x0 << 2)
+#	define CLK_FREQ_19P2MHZ	(0x1 << 2)
+#	define CLK_CTL_D3_LPE	(0x0 << 0)
+#	define CLK_CTL_ON	(0x1 << 0)
+#	define CLK_CTL_OFF	(0x2 << 0)
 
 /* IO Mapped registers behind ACPI_BASE_ADDRESS */
 #define PM1_STS			0x00

src/soc/intel/baytrail/chip.h

@@ -47,6 +47,10 @@ struct soc_intel_baytrail_config {
 	uint32_t usb2_per_port_rcomp_hs_pullup2;
 	uint32_t usb2_per_port_lane3;
 	uint32_t usb2_per_port_rcomp_hs_pullup3;
+
+	/* LPE Audio Clock configuration. */
+	int lpe_codec_clk_freq; /* 19 or 25 are valid. */
+	int lpe_codec_clk_num; /* Platform clock pins. [0:5] are valid. */
 };
 
 extern struct chip_operations soc_intel_baytrail_ops;

src/soc/intel/baytrail/lpe.c

@@ -17,23 +17,60 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
+#include <arch/io.h>
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
 
-#include <baytrail/iosf.h>
+#include <baytrail/iomap.h>
+#include <baytrail/pci_devs.h>
+#include <baytrail/pmc.h>
 #include <baytrail/ramstage.h>
+#include "chip.h"
+
+
+static void setup_codec_clock(device_t dev)
+{
+	uint32_t reg;
+	int clk_reg;
+	struct soc_intel_baytrail_config *config;
+	const char *freq_str;
+
+	config = dev->chip_info;
+	switch (config->lpe_codec_clk_freq) {
+	case 19:
+		freq_str = "19.2";
+		reg = CLK_FREQ_19P2MHZ;
+		break;
+	case 25:
+		freq_str = "25";
+		reg = CLK_FREQ_25MHZ;
+		break;
+	default:
+		printk(BIOS_DEBUG, "LPE codec clock not required.\n");
+		return;
+	}
+
+	/* Default to always running. */
+	reg |= CLK_CTL_ON;
+
+	if (config->lpe_codec_clk_num < 0 || config->lpe_codec_clk_num > 5) {
+		printk(BIOS_DEBUG, "Invalid LPE codec clock number.\n");
+		return;
+	}
+
+	printk(BIOS_DEBUG, "LPE Audio codec clock set to %sMHz.\n", freq_str);
+
+	clk_reg = PMC_BASE_ADDRESS + PLT_CLK_CTL_0;
+	clk_reg += 4 * config->lpe_codec_clk_num;
+
+	write32(clk_reg, (read32(clk_reg) & ~0x7) | reg);
+}
 
 static void lpe_init(device_t dev)
 {
-	uint32_t reg;
+	setup_codec_clock(dev);
-
-	/* Work around for Audio Clock. */
-	reg = iosf_ccu_read(PLT_CLK_CTRL_3);
-	reg &= ~0xff;
-	reg |= PLT_CLK_CTRL_25MHZ_FREQ | PLT_CLK_CTRL_SELECT_FREQ;
-	iosf_ccu_write(PLT_CLK_CTRL_3, reg);
 }
 
 static const struct device_operations device_ops = {