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soc/intel/icelake/acpi: Replace Store(a,b) with ASL 2.0 syntax 

Replace `Store (a, b)` with `b = a`.

Change-Id: I12560d151d26186e1f4eb0165aa8cef33b7a16aa
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70685
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This commit is contained in:
Felix Singer 2022-12-12 07:33:35 +01:00
parent 476fe6ae7e
commit 8cc2962b12
2 changed files with 11 additions and 11 deletions
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6
src/soc/intel/icelake/acpi/pch_hda.asl
View File

@ -56,9 +56,9 @@ Device (HDAS)
CreateQWordField (NBUF, ^NHLT._MAX, NMAS)
CreateQWordField (NBUF, ^NHLT._LEN, NLEN)
Store (NHLA, NBAS)
Store (NHLA, NMAS)
Store (NHLL, NLEN)
NBAS = NHLA
NMAS = NHLA
NLEN = NHLL
Return (NBUF)
}

16
src/soc/intel/icelake/acpi/scs.asl
View File

@ -37,22 +37,22 @@ Scope (\_SB.PCI0) {
Method(_PS0, 0, Serialized) {
Stall (50) // Sleep 50 us
Store(0, PGEN) // Disable PG
PGEN = 0 // Disable PG
/* Clear register 0x1C20/0x4820 */
^^SCSC (PID_EMMC)
/* Set Power State to D0 */
And (PMCR, 0xFFFC, PMCR)
Store (PMCR, ^TEMP)
^TEMP = PMCR
}
Method(_PS3, 0, Serialized) {
Store(1, PGEN) // Enable PG
PGEN = 1 // Enable PG
/* Set Power State to D3 */
Or (PMCR, 0x0003, PMCR)
Store (PMCR, ^TEMP)
^TEMP = PMCR
}
Device (CARD)
@ -90,23 +90,23 @@ Scope (\_SB.PCI0) {
Method (_PS0, 0, Serialized)
{
Store (0, PGEN) /* Disable PG */
PGEN = 0 /* Disable PG */
/* Clear register 0x1C20/0x4820 */
^^SCSC (PID_SDX)
/* Set Power State to D0 */
And (PMCR, 0xFFFC, PMCR)
Store (PMCR, ^TEMP)
^TEMP = PMCR
}
Method (_PS3, 0, Serialized)
{
Store (1, PGEN) /* Enable PG */
PGEN = 1 /* Enable PG */
/* Set Power State to D3 */
Or (PMCR, 0x0003, PMCR)
Store (PMCR, ^TEMP)
^TEMP = PMCR
}
Device (CARD)