util: Add Picasso and Pollock platforms to spd_tools
PCO = Picasso PLK = Pollock BUG=b:162939176 Signed-off-by: Rob Barnes <robbarnes@google.com> Change-Id: I43b74f68871062112f53fbbef8a170db53734b3e Reviewed-on: https://review.coreboot.org/c/coreboot/+/44477 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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# DDR4 SPD tools README
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Tools for generating SPD files for DDR4 memory used in memory down
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configurations on Intel Tiger Lake (TGL) based
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platforms. These tools generate SPDs following JESD79-4C
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Tools for generating SPD files for DDR4 memory used in platforms with
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memory down configuration. These tools generate SPDs following JESD79-4C
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and Jedec 4.1.2.L-5 R29 v103 specifications.
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There are two tools provided that assist TGL based mainboards
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to generate SPDs and Makefile to integrate these SPDs in coreboot
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build. These tools can also be used to allocate DRAM IDs (configure
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DRAM hardware straps) for any DDR4 memory part used by the board.
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There are two tools provided that assist with generating SPDs and Makefiles
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to integrate in coreboot build. These tools can also be used to allocate
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DRAM IDs (configure DRAM hardware straps) for any DDR4 memory part used
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by the board.
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* gen_spd.go: Generates de-duplicated SPD files using a global memory
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part list provided by the mainboard in JSON format. Additionally,
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attributes as per the datasheet. This is the list of all known
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DDR4 memory parts irrespective of their usage on the board.
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* SoC platform name for which the SPDs are being generated. Currently
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supported platform names are `TGL`.
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supported platform names are `TGL`, `PCO` and `PLK`.
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Input JSON file requires the following two fields for every memory part:
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* `name`: Name of the memory part
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SPDManifestFileName = "spd_manifest.generated.txt"
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PlatformTGL = 0
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PlatformPCO = 1
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PlatformPLK = 2
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)
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var platformMap = map[string]int {
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"TGL": PlatformTGL,
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"PCO": PlatformPCO,
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"PLK": PlatformPLK,
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}
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var currPlatform int
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