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merge minor solo changes 

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1235 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer 2003-10-27 14:54:19 +00:00
parent 5484eb6b43
commit 8ccc6c23b3
2 changed files with 10 additions and 11 deletions
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13
src/mainboard/amd/solo/Config.lb
View File

@ -42,7 +42,7 @@ option IRQ_SLOT_COUNT=7
## Build code to export an x86 MP table
## Useful for specifying IRQ routing values
##
option HAVE_MP_TABLE=0
option HAVE_MP_TABLE=1
##
## Build code to export a CMOS option table
@ -52,7 +52,7 @@ option HAVE_OPTION_TABLE=1
##
## AMD Solo is a 1cpu board
##
option CONFIG_SMP=0
option CONFIG_SMP=1
option CONFIG_MAX_CPUS=1
##
@ -135,7 +135,7 @@ arch i386 end
##
driver mainboard.o
# if HAVE_MP_TABLE object mptable.o end
if HAVE_MP_TABLE object mptable.o end
if HAVE_PIRQ_TABLE object irq_tables.o end
object reset.o
@ -238,12 +238,12 @@ northbridge amd/amdk8 "mc0"
pci 0:1.1 on
pci 0:1.2 on
pci 0:1.3 on
pci 0:1.5 off
pci 0:1.6 off
pci 0:1.5 on
pci 0:1.6 on
pci 1:0.0 on
pci 1:0.1 on
pci 1:0.2 on
pci 1:1.0 off
pci 1:1.0 on
superio NSC/pc87360 link 1
pnp 2e.0
pnp 2e.1
@ -263,7 +263,6 @@ northbridge amd/amdk8 "mc0"
end
cpu k8 "cpu0"
register "up" = "{ .chip = &amd8111, .ht_width=16, .ht_speed=600 }"
end
##

6
targets/amd/solo/Config.lb
View File

@ -54,8 +54,8 @@ option CC="gcc -m32"
option CONFIG_CHIP_CONFIGURE=1
option MAXIMUM_CONSOLE_LOGLEVEL=8
option DEFAULT_CONSOLE_LOGLEVEL=8
option MAXIMUM_CONSOLE_LOGLEVEL=10
option DEFAULT_CONSOLE_LOGLEVEL=10
option CONFIG_CONSOLE_SERIAL8250=1
option CPU_FIXUP=1
@ -99,4 +99,4 @@ romimage "fallback"
payload /suse/stepan/tg3--ide_disk.zelf
end
buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
buildrom ./solo.rom ROM_SIZE "normal" "fallback"