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nb/amd/pi/00730F01: add CPU and domain ops in devicetree 

Add the CPU and PCI domain operation bindings statically in the chipset
devicetree instead of adding them during runtime.

TEST=PC Engines APU2 still boots and doesn't show any new problems

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I44fa57458c408e74a6341643620c5e9ac1817557
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79085
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Felix Held 2023-11-16 00:58:30 +01:00
parent 1952d13a41
commit 8ccd314ce6
2 changed files with 6 additions and 14 deletions
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5
src/northbridge/amd/pi/00730F01/chipset.cb
View File

@ -1,9 +1,12 @@
# SPDX-License-Identifier: GPL-2.0-only # SPDX-License-Identifier: GPL-2.0-only
chip northbridge/amd/pi/00730F01 chip northbridge/amd/pi/00730F01
device cpu_cluster 0 on end device cpu_cluster 0 on
ops amd_fam16_mod30_cpu_bus_ops
end
device domain 0 on device domain 0 on
ops amd_fam16_mod30_pci_domain_ops
device pci 0.0 alias gnb on end device pci 0.0 alias gnb on end
device pci 0.2 alias iommu off end device pci 0.2 alias iommu off end
device pci 1.0 alias gfx off end device pci 1.0 alias gfx off end

15
src/northbridge/amd/pi/00730F01/northbridge.c
View File

@ -831,7 +831,7 @@ static const char *domain_acpi_name(const struct device *dev)
return NULL; return NULL;
} }
static struct device_operations pci_domain_ops = { struct device_operations amd_fam16_mod30_pci_domain_ops = {
.read_resources = domain_read_resources, .read_resources = domain_read_resources,
.set_resources = pci_domain_set_resources, .set_resources = pci_domain_set_resources,
.scan_bus = pci_host_bridge_scan_bus, .scan_bus = pci_host_bridge_scan_bus,
@ -863,26 +863,15 @@ void generate_cpu_entries(const struct device *device)
} }
} }
static struct device_operations cpu_bus_ops = { struct device_operations amd_fam16_mod30_cpu_bus_ops = {
.read_resources = noop_read_resources, .read_resources = noop_read_resources,
.set_resources = noop_set_resources, .set_resources = noop_set_resources,
.init = mp_cpu_bus_init, .init = mp_cpu_bus_init,
.acpi_fill_ssdt = generate_cpu_entries, .acpi_fill_ssdt = generate_cpu_entries,
}; };
static void root_complex_enable_dev(struct device *dev)
{
/* Set the operations if it is a special bus type */
if (dev->path.type == DEVICE_PATH_DOMAIN) {
dev->ops = &pci_domain_ops;
} else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
dev->ops = &cpu_bus_ops;
}
}
struct chip_operations northbridge_amd_pi_00730F01_ops = { struct chip_operations northbridge_amd_pi_00730F01_ops = {
CHIP_NAME("AMD FAM16 Root Complex") CHIP_NAME("AMD FAM16 Root Complex")
.enable_dev = root_complex_enable_dev,
.final = fam16_finalize, .final = fam16_finalize,
}; };