nb/amd/pi/00730F01: add CPU and domain ops in devicetree
Add the CPU and PCI domain operation bindings statically in the chipset devicetree instead of adding them during runtime. TEST=PC Engines APU2 still boots and doesn't show any new problems Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I44fa57458c408e74a6341643620c5e9ac1817557 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79085 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
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@ -1,9 +1,12 @@
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# SPDX-License-Identifier: GPL-2.0-only
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chip northbridge/amd/pi/00730F01
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device cpu_cluster 0 on end
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device cpu_cluster 0 on
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ops amd_fam16_mod30_cpu_bus_ops
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end
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device domain 0 on
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ops amd_fam16_mod30_pci_domain_ops
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device pci 0.0 alias gnb on end
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device pci 0.2 alias iommu off end
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device pci 1.0 alias gfx off end
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@ -831,7 +831,7 @@ static const char *domain_acpi_name(const struct device *dev)
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return NULL;
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}
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static struct device_operations pci_domain_ops = {
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struct device_operations amd_fam16_mod30_pci_domain_ops = {
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.read_resources = domain_read_resources,
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.set_resources = pci_domain_set_resources,
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.scan_bus = pci_host_bridge_scan_bus,
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@ -863,26 +863,15 @@ void generate_cpu_entries(const struct device *device)
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}
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}
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static struct device_operations cpu_bus_ops = {
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struct device_operations amd_fam16_mod30_cpu_bus_ops = {
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.read_resources = noop_read_resources,
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.set_resources = noop_set_resources,
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.init = mp_cpu_bus_init,
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.acpi_fill_ssdt = generate_cpu_entries,
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};
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static void root_complex_enable_dev(struct device *dev)
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{
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/* Set the operations if it is a special bus type */
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if (dev->path.type == DEVICE_PATH_DOMAIN) {
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dev->ops = &pci_domain_ops;
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} else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
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dev->ops = &cpu_bus_ops;
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}
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}
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struct chip_operations northbridge_amd_pi_00730F01_ops = {
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CHIP_NAME("AMD FAM16 Root Complex")
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.enable_dev = root_complex_enable_dev,
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.final = fam16_finalize,
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};
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