From 8cced29eed33285e0a086231c567f4633372f004 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Wed, 11 Sep 2019 10:32:31 +0530 Subject: [PATCH] =?UTF-8?q?soc/intel/cnl:=20Remove=20unnecessary=20FSP=20U?= =?UTF-8?q?PD=20=E2=80=9CPchPwrOptEnable=E2=80=9D=20usage?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit PchPwrOptEnable FSP UPD is for internal testing and not really available in externally released FSP source hence assigning this UPD using devicetree config dmipwroptimize doesn't do anything. TEST=Build and boot sarien/arcada. Change-Id: I6da2a088fb697e57d12008fa18bd1764b3da7765 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/35323 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh Reviewed-by: V Sowmya --- .../google/drallion/variants/arcada_cml/devicetree.cb | 1 - src/mainboard/google/drallion/variants/drallion/devicetree.cb | 1 - .../google/drallion/variants/sarien_cml/devicetree.cb | 1 - src/mainboard/google/sarien/variants/arcada/devicetree.cb | 1 - src/mainboard/google/sarien/variants/sarien/devicetree.cb | 1 - src/soc/intel/cannonlake/chip.h | 3 --- src/soc/intel/cannonlake/fsp_params.c | 1 - 7 files changed, 9 deletions(-) diff --git a/src/mainboard/google/drallion/variants/arcada_cml/devicetree.cb b/src/mainboard/google/drallion/variants/arcada_cml/devicetree.cb index 3628264f8a..7050b1ef6e 100644 --- a/src/mainboard/google/drallion/variants/arcada_cml/devicetree.cb +++ b/src/mainboard/google/drallion/variants/arcada_cml/devicetree.cb @@ -32,7 +32,6 @@ chip soc/intel/cannonlake register "psys_pmax" = "140" register "s0ix_enable" = "1" register "dptf_enable" = "1" - register "dmipwroptimize" = "1" register "satapwroptimize" = "1" register "tdp_pl1_override" = "25" register "tdp_pl2_override" = "51" diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index d8ef7a9d2f..d824a552d0 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -32,7 +32,6 @@ chip soc/intel/cannonlake register "psys_pmax" = "140" register "s0ix_enable" = "1" register "dptf_enable" = "1" - register "dmipwroptimize" = "1" register "satapwroptimize" = "1" register "tdp_pl1_override" = "25" register "tdp_pl2_override" = "51" diff --git a/src/mainboard/google/drallion/variants/sarien_cml/devicetree.cb b/src/mainboard/google/drallion/variants/sarien_cml/devicetree.cb index 84aacd58ec..f2367ffa1d 100644 --- a/src/mainboard/google/drallion/variants/sarien_cml/devicetree.cb +++ b/src/mainboard/google/drallion/variants/sarien_cml/devicetree.cb @@ -34,7 +34,6 @@ chip soc/intel/cannonlake register "speed_shift_enable" = "1" register "s0ix_enable" = "1" register "dptf_enable" = "1" - register "dmipwroptimize" = "1" register "satapwroptimize" = "1" register "AcousticNoiseMitigation" = "1" register "SlowSlewRateForIa" = "2" diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index ebcf140b4c..0f3023cace 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -32,7 +32,6 @@ chip soc/intel/cannonlake register "psys_pmax" = "140" register "s0ix_enable" = "1" register "dptf_enable" = "1" - register "dmipwroptimize" = "1" register "satapwroptimize" = "1" register "tdp_pl1_override" = "25" register "tdp_pl2_override" = "51" diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index d3aab62a68..cd216e593b 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -34,7 +34,6 @@ chip soc/intel/cannonlake register "speed_shift_enable" = "1" register "s0ix_enable" = "1" register "dptf_enable" = "1" - register "dmipwroptimize" = "1" register "satapwroptimize" = "1" register "AcousticNoiseMitigation" = "1" register "SlowSlewRateForIa" = "2" diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 9c7c17147e..451c920fae 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -387,9 +387,6 @@ struct soc_intel_cannonlake_config { uint8_t SlowSlewRateForSa; uint8_t SlowSlewRateForFivr; - /* DMI Power Optimizer */ - uint8_t dmipwroptimize; - /* SATA Power Optimizer */ uint8_t satapwroptimize; diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index f48a626be9..76d40aa624 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -377,7 +377,6 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->FastPkgCRampDisableFivr = config->FastPkgCRampDisableFivr; /* Power Optimizer */ - params->PchPwrOptEnable = config->dmipwroptimize; params->SataPwrOptEnable = config->satapwroptimize; /* Disable PCH ACPI timer */