mb/google/nissa/var/gothrax: Supplement register settings for SX9324 P-sensor
Set the following register value to make SX9324 work normally "ph0_pin" = "{1, 3, 3}" "ph1_pin" = "{3, 2, 1}" "ph2_pin" = "{3, 3, 1}" "ph3_pin" = "{1, 3, 3}" "ph01_resolution" = "512" "ph23_resolution" = "1024" "startup_sensor" = "1" "ph01_proxraw_strength" = "2" "ph23_proxraw_strength" = "2" "avg_pos_strength" = "256" "cs_idle_sleep" = ""gnd"" "int_comp_resistor" = ""lowest"" "input_precharge_resistor_ohms" = "4000" "input_analog_gain" = "3" BUG=b:295109511 BRANCH=None TEST=emerge-nissa coreboot chromeos-bootimage & Check sar sensor data Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com> Change-Id: Ib15f12d754fec8b379afd702b27d0701fac78072 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78463 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Derek Huang <derekhuang@google.com>
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@ -271,6 +271,21 @@ chip soc/intel/alderlake
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register "reg_adv_ctrl18" = "0x33"
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register "reg_adv_ctrl18" = "0x33"
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register "reg_adv_ctrl19" = "0xf0"
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register "reg_adv_ctrl19" = "0xf0"
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register "reg_adv_ctrl20" = "0xf0"
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register "reg_adv_ctrl20" = "0xf0"
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register "ph0_pin" = "{1, 3, 3}"
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register "ph1_pin" = "{3, 2, 1}"
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register "ph2_pin" = "{3, 3, 1}"
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register "ph3_pin" = "{1, 3, 3}"
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register "ph01_resolution" = "512"
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register "ph23_resolution" = "1024"
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register "startup_sensor" = "1"
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register "ph01_proxraw_strength" = "2"
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register "ph23_proxraw_strength" = "2"
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register "avg_pos_strength" = "256"
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register "cs_idle_sleep" = ""gnd""
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register "int_comp_resistor" = ""lowest""
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register "input_precharge_resistor_ohms" = "4000"
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register "input_analog_gain" = "3"
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device i2c 28 on end
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device i2c 28 on end
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end
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end
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end
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end
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