haswell: add multipurpose SMM memory region
The SMM region is available for multipurpose use before the SMM handler is relocated. Provide a configurable sized region in the TSEG for use before the SMM handler is relocated. This feature is implemented by making the reserved size a Kconfig option. Also make the IED region a Kconfig option as well. Lastly add some sanity checking on the Kconfig options. Change-Id: Idd7fccf925a8787146906ac766b7878845c75935 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2804 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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@ -29,6 +29,14 @@ config SMM_TSEG_SIZE
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hex
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default 0x800000
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config IED_REGION_SIZE
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hex
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default 0x400000
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config SMM_RESERVED_SIZE
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hex
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default 0x100000
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config MICROCODE_INCLUDE_PATH
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string
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default "src/cpu/intel/haswell"
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@ -100,6 +100,26 @@
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#define PSS_LATENCY_TRANSITION 10
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#define PSS_LATENCY_BUSMASTER 10
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/* Region of SMM space is reserved for multipurpose use. It falls below
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* the IED region and above the SMM handler. */
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#define RESERVED_SMM_SIZE CONFIG_SMM_RESERVED_SIZE
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#define RESERVED_SMM_OFFSET \
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(CONFIG_SMM_TSEG_SIZE - CONFIG_IED_REGION_SIZE - RESERVED_SMM_SIZE)
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/* Sanity check config options. */
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#if (CONFIG_SMM_TSEG_SIZE <= (CONFIG_IED_REGION_SIZE + RESERVED_SMM_SIZE))
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# error "CONFIG_SMM_TSEG_SIZE <= (CONFIG_IED_REGION_SIZE + RESERVED_SMM_SIZE)"
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#endif
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#if (CONFIG_SMM_TSEG_SIZE < 0x800000)
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# error "CONFIG_SMM_TSEG_SIZE must at least be 8MiB"
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#endif
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#if ((CONFIG_SMM_TSEG_SIZE & (CONFIG_SMM_TSEG_SIZE - 1)) != 0)
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# error "CONFIG_SMM_TSEG_SIZE is not a power of 2"
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#endif
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#if ((CONFIG_IED_REGION_SIZE & (CONFIG_IED_REGION_SIZE - 1)) != 0)
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# error "CONFIG_IED_REGION_SIZE is not a power of 2"
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#endif
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#ifndef __ROMCC__
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#if defined(__PRE_RAM__)
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@ -258,6 +258,9 @@ static void fill_in_relocation_params(device_t dev,
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params->ied_base = tsegmb + params->smram_size;
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params->ied_size = tseg_size - params->smram_size;
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/* Adjust available SMM handler memory size. */
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params->smram_size -= RESERVED_SMM_SIZE;
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/* SMRR has 32-bits of valid address aligned to 4KiB. */
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params->smrr_base.lo = (params->smram_base & rmask) | MTRR_TYPE_WRBACK;
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params->smrr_base.hi = 0;
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@ -43,8 +43,8 @@
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#define IVB_STEP_K0 (BASE_REV_IVB + 5)
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#define IVB_STEP_D0 (BASE_REV_IVB + 6)
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/* Intel Enhanced Debug region must be 4MB */
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#define IED_SIZE 0x400000
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/* Intel Enhanced Debug region */
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#define IED_SIZE CONFIG_IED_REGION_SIZE
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/* Northbridge BARs */
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#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS /* 4 KB per PCIe device */
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