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haswell: add multipurpose SMM memory region 

The SMM region is available for multipurpose use before the SMM
handler is relocated. Provide a configurable sized region in the
TSEG for use before the SMM handler is relocated. This feature is
implemented by making the reserved size a Kconfig option. Also
make the IED region a Kconfig option as well. Lastly add some sanity
checking on the Kconfig options.

Change-Id: Idd7fccf925a8787146906ac766b7878845c75935
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2804
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This commit is contained in:
Aaron Durbin 2013-02-15 21:45:06 -06:00 committed by Ronald G. Minnich
parent 67481ddc2e
commit 8ce667e506
4 changed files with 33 additions and 2 deletions
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8
src/cpu/intel/haswell/Kconfig
View File

@ -29,6 +29,14 @@ config SMM_TSEG_SIZE
hex hex
default 0x800000 default 0x800000
config IED_REGION_SIZE
hex
default 0x400000
config SMM_RESERVED_SIZE
hex
default 0x100000
config MICROCODE_INCLUDE_PATH config MICROCODE_INCLUDE_PATH
string string
default "src/cpu/intel/haswell" default "src/cpu/intel/haswell"

20
src/cpu/intel/haswell/haswell.h
View File

@ -100,6 +100,26 @@
#define PSS_LATENCY_TRANSITION 10 #define PSS_LATENCY_TRANSITION 10
#define PSS_LATENCY_BUSMASTER 10 #define PSS_LATENCY_BUSMASTER 10
/* Region of SMM space is reserved for multipurpose use. It falls below
* the IED region and above the SMM handler. */
#define RESERVED_SMM_SIZE CONFIG_SMM_RESERVED_SIZE
#define RESERVED_SMM_OFFSET \
(CONFIG_SMM_TSEG_SIZE - CONFIG_IED_REGION_SIZE - RESERVED_SMM_SIZE)
/* Sanity check config options. */
#if (CONFIG_SMM_TSEG_SIZE <= (CONFIG_IED_REGION_SIZE + RESERVED_SMM_SIZE))
# error "CONFIG_SMM_TSEG_SIZE <= (CONFIG_IED_REGION_SIZE + RESERVED_SMM_SIZE)"
#endif
#if (CONFIG_SMM_TSEG_SIZE < 0x800000)
# error "CONFIG_SMM_TSEG_SIZE must at least be 8MiB"
#endif
#if ((CONFIG_SMM_TSEG_SIZE & (CONFIG_SMM_TSEG_SIZE - 1)) != 0)
# error "CONFIG_SMM_TSEG_SIZE is not a power of 2"
#endif
#if ((CONFIG_IED_REGION_SIZE & (CONFIG_IED_REGION_SIZE - 1)) != 0)
# error "CONFIG_IED_REGION_SIZE is not a power of 2"
#endif
#ifndef __ROMCC__ #ifndef __ROMCC__
#if defined(__PRE_RAM__) #if defined(__PRE_RAM__)

3
src/cpu/intel/haswell/smmrelocate.c
View File

@ -258,6 +258,9 @@ static void fill_in_relocation_params(device_t dev,
params->ied_base = tsegmb + params->smram_size; params->ied_base = tsegmb + params->smram_size;
params->ied_size = tseg_size - params->smram_size; params->ied_size = tseg_size - params->smram_size;
/* Adjust available SMM handler memory size. */
params->smram_size -= RESERVED_SMM_SIZE;
/* SMRR has 32-bits of valid address aligned to 4KiB. */ /* SMRR has 32-bits of valid address aligned to 4KiB. */
params->smrr_base.lo = (params->smram_base & rmask) | MTRR_TYPE_WRBACK; params->smrr_base.lo = (params->smram_base & rmask) | MTRR_TYPE_WRBACK;
params->smrr_base.hi = 0; params->smrr_base.hi = 0;

4
src/northbridge/intel/haswell/haswell.h
View File

@ -43,8 +43,8 @@
#define IVB_STEP_K0 (BASE_REV_IVB + 5) #define IVB_STEP_K0 (BASE_REV_IVB + 5)
#define IVB_STEP_D0 (BASE_REV_IVB + 6) #define IVB_STEP_D0 (BASE_REV_IVB + 6)
/* Intel Enhanced Debug region must be 4MB */ /* Intel Enhanced Debug region */
#define IED_SIZE 0x400000 #define IED_SIZE CONFIG_IED_REGION_SIZE
/* Northbridge BARs */ /* Northbridge BARs */
#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS /* 4 KB per PCIe device */ #define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS /* 4 KB per PCIe device */