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vc/amd/fsp/picasso: update UPD header 

A new version of UPD headers generated from the FSP tree. This adds UPDs
for downcoring and increases the number of DXIO descriptor slots.

BUG=b:161152720
TEST=SATA on Mandolin works now.

Cq-Depend: chrome-internal:3175393

Change-Id: I1e27597e22af4df65d206a38b67c4920298b30b2
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43659
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Felix Held 2020-07-21 01:58:32 +02:00
parent 4eed5e9057
commit 8ced938763
2 changed files with 26 additions and 25 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
src/vendorcode/amd/fsp/picasso/FspmUpd.h
View File

@ -61,7 +61,10 @@ typedef struct __packed {
/** Offset 0x00CE**/ uint8_t unused8; /** Offset 0x00CE**/ uint8_t unused8;
/** Offset 0x00CF**/ uint8_t unused9; /** Offset 0x00CF**/ uint8_t unused9;
/** Offset 0x00D0**/ uint32_t bert_size; /** Offset 0x00D0**/ uint32_t bert_size;
/** Offset 0x00D4**/ uint8_t UnusedUpdSpace0[44]; /** Offset 0x00D4**/ uint8_t UnusedUpdSpace0;
/** Offset 0x00D5**/ uint8_t ccx_down_core_mode;
/** Offset 0x00D6**/ uint8_t ccx_disable_smt;
/** Offset 0x00D7**/ uint8_t UnusedUpdSpace1[41];
/** Offset 0x0100**/ uint16_t Reserved100; /** Offset 0x0100**/ uint16_t Reserved100;
/** Offset 0x0102**/ uint16_t UpdTerminator; /** Offset 0x0102**/ uint16_t UpdTerminator;
} FSP_M_CONFIG; } FSP_M_CONFIG;

46
src/vendorcode/amd/fsp/picasso/FspsUpd.h
View File

@ -9,36 +9,34 @@
#include <FspUpd.h> #include <FspUpd.h>
#define FSPS_UPD_DXIO_DESCRIPTOR_COUNT 6 #define FSPS_UPD_DXIO_DESCRIPTOR_COUNT 8
#define FSPS_UPD_DDI_DESCRIPTOR_COUNT 4 #define FSPS_UPD_DDI_DESCRIPTOR_COUNT 4
typedef struct __packed { typedef struct __packed {
/** Offset 0x0020**/ uint32_t emmc0_mode; /** Offset 0x0020**/ uint32_t emmc0_mode;
/** Offset 0x0024**/ uint8_t unused0[12]; /** Offset 0x0024**/ uint8_t unused0[12];
/** Offset 0x0030**/ uint8_t dxio_descriptor[FSPS_UPD_DXIO_DESCRIPTOR_COUNT][16]; /** Offset 0x0030**/ uint8_t dxio_descriptor[FSPS_UPD_DXIO_DESCRIPTOR_COUNT][16];
/** Offset 0x0090**/ uint32_t ddi_descriptor[FSPS_UPD_DDI_DESCRIPTOR_COUNT]; /** Offset 0x00B0**/ uint8_t unused1[16];
/** Offset 0x00A0**/ uint32_t unused1; /** Offset 0x00C0**/ uint32_t ddi_descriptor[FSPS_UPD_DDI_DESCRIPTOR_COUNT];
/** Offset 0x00A4**/ uint32_t unused2; /** Offset 0x00D0**/ uint8_t unused2[16];
/** Offset 0x00A8**/ uint32_t unused3; /** Offset 0x00E0**/ uint8_t fch_usb_version_major;
/** Offset 0x00AC**/ uint32_t unused4; /** Offset 0x00E1**/ uint8_t fch_usb_version_minor;
/** Offset 0x00B0**/ uint8_t fch_usb_version_major; /** Offset 0x00E2**/ uint8_t fch_usb_2_port0_phy_tune[9];
/** Offset 0x00B1**/ uint8_t fch_usb_version_minor; /** Offset 0x00EB**/ uint8_t fch_usb_2_port1_phy_tune[9];
/** Offset 0x00B2**/ uint8_t fch_usb_2_port0_phy_tune[9]; /** Offset 0x00F4**/ uint8_t fch_usb_2_port2_phy_tune[9];
/** Offset 0x00BB**/ uint8_t fch_usb_2_port1_phy_tune[9]; /** Offset 0x00FD**/ uint8_t fch_usb_2_port3_phy_tune[9];
/** Offset 0x00C4**/ uint8_t fch_usb_2_port2_phy_tune[9]; /** Offset 0x0106**/ uint8_t fch_usb_2_port4_phy_tune[9];
/** Offset 0x00CD**/ uint8_t fch_usb_2_port3_phy_tune[9]; /** Offset 0x010F**/ uint8_t fch_usb_2_port5_phy_tune[9];
/** Offset 0x00D6**/ uint8_t fch_usb_2_port4_phy_tune[9]; /** Offset 0x0118**/ uint8_t fch_usb_device_removable;
/** Offset 0x00DF**/ uint8_t fch_usb_2_port5_phy_tune[9]; /** Offset 0x0119**/ uint8_t fch_usb_3_port_force_gen1;
/** Offset 0x00E8**/ uint8_t fch_usb_device_removable; /** Offset 0x011A**/ uint8_t fch_usb_u3_rx_det_wa_enable;
/** Offset 0x00E9**/ uint8_t fch_usb_3_port_force_gen1; /** Offset 0x011B**/ uint8_t fch_usb_u3_rx_det_wa_portmap;
/** Offset 0x00EA**/ uint8_t fch_usb_u3_rx_det_wa_enable; /** Offset 0x011C**/ uint8_t fch_usb_early_debug_select_enable;
/** Offset 0x00EB**/ uint8_t fch_usb_u3_rx_det_wa_portmap; /** Offset 0x011D**/ uint8_t unused3;
/** Offset 0x00EC**/ uint8_t fch_usb_early_debug_select_enable; /** Offset 0x011E**/ uint32_t xhci_oc_pin_select;
/** Offset 0x00ED**/ uint8_t unused8; /** Offset 0x0122**/ uint8_t xhci0_force_gen1;
/** Offset 0x00EE**/ uint32_t xhci_oc_pin_select; /** Offset 0x0123**/ uint8_t UnusedUpdSpace0[45];
/** Offset 0x00F2**/ uint8_t xhci0_force_gen1; /** Offset 0x0150**/ uint16_t UpdTerminator;
/** Offset 0x00F3**/ uint8_t UnusedUpdSpace0[45];
/** Offset 0x0120**/ uint16_t UpdTerminator;
} FSP_S_CONFIG; } FSP_S_CONFIG;
/** Fsp S UPD Configuration /** Fsp S UPD Configuration