sb/amd/{agesa,pi}/hudson: add southbridge C bootblock initialization
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Iaba5443d8770473c4abe73ec2a91f8d6a52574af Reviewed-on: https://review.coreboot.org/c/coreboot/+/37168 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Michał Żygowski
Kyösti Mälkki
parent
55009af42c
commit
8cee45c3f8
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@ -17,7 +17,12 @@ ramstage-y += sd.c
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ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c
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ramstage-y += reset.c
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bootblock-y += enable_usbdebug.c
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ifneq ($(CONFIG_ROMCC_BOOTBLOCK),y)
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bootblock-y += bootblock.c
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bootblock-y += early_setup.c
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bootblock-$(CONFIG_USBDEBUG) += enable_usbdebug.c
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endif
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romstage-y += enable_usbdebug.c
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ramstage-y += enable_usbdebug.c
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romstage-y += early_setup.c
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@ -60,3 +60,48 @@ static void bootblock_southbridge_init(void)
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{
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hudson_enable_rom();
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}
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#if !CONFIG(ROMCC_BOOTBLOCK)
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#include <bootblock_common.h>
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#include <amdblocks/acpimmio.h>
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#include <southbridge/amd/agesa/hudson/hudson.h>
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void bootblock_soc_early_init(void)
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{
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pci_devfn_t dev;
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u32 data;
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bootblock_southbridge_init();
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hudson_lpc_decode();
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enable_acpimmio_decode_pm24();
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dev = PCI_DEV(0, 0x14, 3);
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data = pci_read_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE);
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/* enable 0x2e/0x4e IO decoding for SuperIO */
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pci_write_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE, data | 3);
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/*
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* Enable FCH to decode TPM associated Memory and IO regions for vboot
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*
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* Enable decoding of TPM cycles defined in TPM 1.2 spec
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* Enable decoding of legacy TPM addresses: IO addresses 0x7f-
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* 0x7e and 0xef-0xee.
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*/
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data = pci_read_config32(dev, LPC_TRUSTED_PLATFORM_MODULE);
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data |= TPM_12_EN | TPM_LEGACY_EN;
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pci_write_config32(dev, LPC_TRUSTED_PLATFORM_MODULE, data);
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/*
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* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
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* LpcClk[1:0]". This following register setting has been
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* replicated in every reference design since Parmer, so it is
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* believed to be required even though it is not documented in
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* the SoC BKDGs. Without this setting, there is no serial
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* output.
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*/
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pm_write8(0xd2, 0);
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}
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#endif
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@ -87,4 +87,22 @@ void hudson_lpc_port80(void)
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pci_write_config8(dev, 0x4a, byte);
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}
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void hudson_lpc_decode(void)
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{
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pci_devfn_t dev;
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u32 tmp;
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dev = PCI_DEV(0, 0x14, 3);
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/* Serial port numeration on Hudson:
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* PORT0 - 0x3f8
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* PORT1 - 0x2f8
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* PORT5 - 0x2e8
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* PORT7 - 0x3e8
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*/
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tmp = DECODE_ENABLE_SERIAL_PORT0 | DECODE_ENABLE_SERIAL_PORT1
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| DECODE_ENABLE_SERIAL_PORT5 | DECODE_ENABLE_SERIAL_PORT7;
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pci_write_config32(dev, LPC_IO_PORT_DECODE_ENABLE, tmp);
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}
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#endif /* _HUDSON_EARLY_SETUP_C_ */
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@ -45,6 +45,46 @@
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#define REV_HUDSON_A11 0x11
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#define REV_HUDSON_A12 0x12
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#define LPC_IO_PORT_DECODE_ENABLE 0x44
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#define DECODE_ENABLE_PARALLEL_PORT0 BIT(0)
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#define DECODE_ENABLE_PARALLEL_PORT1 BIT(1)
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#define DECODE_ENABLE_PARALLEL_PORT2 BIT(2)
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#define DECODE_ENABLE_PARALLEL_PORT3 BIT(3)
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#define DECODE_ENABLE_PARALLEL_PORT4 BIT(4)
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#define DECODE_ENABLE_PARALLEL_PORT5 BIT(5)
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#define DECODE_ENABLE_SERIAL_PORT0 BIT(6)
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#define DECODE_ENABLE_SERIAL_PORT1 BIT(7)
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#define DECODE_ENABLE_SERIAL_PORT2 BIT(8)
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#define DECODE_ENABLE_SERIAL_PORT3 BIT(9)
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#define DECODE_ENABLE_SERIAL_PORT4 BIT(10)
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#define DECODE_ENABLE_SERIAL_PORT5 BIT(11)
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#define DECODE_ENABLE_SERIAL_PORT6 BIT(12)
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#define DECODE_ENABLE_SERIAL_PORT7 BIT(13)
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#define DECODE_ENABLE_AUDIO_PORT0 BIT(14)
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#define DECODE_ENABLE_AUDIO_PORT1 BIT(15)
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#define DECODE_ENABLE_AUDIO_PORT2 BIT(16)
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#define DECODE_ENABLE_AUDIO_PORT3 BIT(17)
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#define DECODE_ENABLE_MIDI_PORT0 BIT(18)
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#define DECODE_ENABLE_MIDI_PORT1 BIT(19)
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#define DECODE_ENABLE_MIDI_PORT2 BIT(20)
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#define DECODE_ENABLE_MIDI_PORT3 BIT(21)
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#define DECODE_ENABLE_MSS_PORT0 BIT(22)
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#define DECODE_ENABLE_MSS_PORT1 BIT(23)
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#define DECODE_ENABLE_MSS_PORT2 BIT(24)
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#define DECODE_ENABLE_MSS_PORT3 BIT(25)
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#define DECODE_ENABLE_FDC_PORT0 BIT(26)
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#define DECODE_ENABLE_FDC_PORT1 BIT(27)
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#define DECODE_ENABLE_GAME_PORT BIT(28)
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#define DECODE_ENABLE_KBC_PORT BIT(29)
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#define DECODE_ENABLE_ACPIUC_PORT BIT(30)
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#define DECODE_ENABLE_ADLIB_PORT BIT(31)
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#define LPC_IO_OR_MEM_DECODE_ENABLE 0x48
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#define LPC_TRUSTED_PLATFORM_MODULE 0x7c
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#define TPM_12_EN BIT(0)
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#define TPM_LEGACY_EN BIT(2)
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#define SPIROM_BASE_ADDRESS_REGISTER 0xA0
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#define SPI_ROM_ENABLE 0x02
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#define SPI_BASE_ADDRESS 0xFEC10000
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@ -63,6 +103,7 @@ static inline int hudson_ide_enable(void)
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void hudson_lpc_port80(void);
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void hudson_pci_port80(void);
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void hudson_lpc_decode(void);
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void hudson_clk_output_48Mhz(void);
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void hudson_enable(struct device *dev);
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@ -28,7 +28,11 @@
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#
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#*****************************************************************************
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bootblock-y += enable_usbdebug.c
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ifneq ($(CONFIG_ROMCC_BOOTBLOCK),y)
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bootblock-y += bootblock.c
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bootblock-y += early_setup.c
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bootblock-$(CONFIG_USBDEBUG) += enable_usbdebug.c
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endif
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romstage-y += early_setup.c
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romstage-y += enable_usbdebug.c
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@ -60,3 +60,50 @@ static void bootblock_southbridge_init(void)
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{
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hudson_enable_rom();
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}
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#if !CONFIG(ROMCC_BOOTBLOCK)
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#include <bootblock_common.h>
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#include <amdblocks/acpimmio.h>
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#include <southbridge/amd/pi/hudson/hudson.h>
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void bootblock_soc_early_init(void)
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{
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pci_devfn_t dev;
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u32 data;
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bootblock_southbridge_init();
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hudson_lpc_decode();
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if (CONFIG(SOUTHBRIDGE_AMD_PI_BOLTON))
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enable_acpimmio_decode_pm24();
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else
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enable_acpimmio_decode_pm04();
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dev = PCI_DEV(0, 0x14, 3);
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data = pci_read_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE);
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/* enable 0x2e/0x4e IO decoding for SuperIO */
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pci_write_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE, data | 3);
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/*
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* Enable FCH to decode TPM associated Memory and IO regions for vboot
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*
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* Enable decoding of TPM cycles defined in TPM 1.2 spec
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* Enable decoding of legacy TPM addresses: IO addresses 0x7f-
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* 0x7e and 0xef-0xee.
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*/
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data = pci_read_config32(dev, LPC_TRUSTED_PLATFORM_MODULE);
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data |= TPM_12_EN | TPM_LEGACY_EN;
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pci_write_config32(dev, LPC_TRUSTED_PLATFORM_MODULE, data);
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/*
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* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
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* LpcClk[1:0]". This following register setting has been
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* replicated in every reference design since Parmer, so it is
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* believed to be required even though it is not documented in
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* the SoC BKDGs. Without this setting, there is no serial
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* output.
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*/
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pm_write8(0xd2, 0);
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}
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#endif
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@ -123,22 +123,17 @@ void hudson_lpc_port80(void)
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void hudson_lpc_decode(void)
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{
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pci_devfn_t dev;
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u32 tmp = 0;
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u32 tmp;
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/* Enable I/O decode to LPC bus */
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dev = PCI_DEV(0, PCU_DEV, LPC_FUNC);
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tmp = DECODE_ENABLE_PARALLEL_PORT0 | DECODE_ENABLE_PARALLEL_PORT2
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| DECODE_ENABLE_PARALLEL_PORT4 | DECODE_ENABLE_SERIAL_PORT0
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| DECODE_ENABLE_SERIAL_PORT1 | DECODE_ENABLE_SERIAL_PORT2
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| DECODE_ENABLE_SERIAL_PORT3 | DECODE_ENABLE_SERIAL_PORT4
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| DECODE_ENABLE_SERIAL_PORT5 | DECODE_ENABLE_SERIAL_PORT6
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| DECODE_ENABLE_SERIAL_PORT7 | DECODE_ENABLE_AUDIO_PORT0
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| DECODE_ENABLE_AUDIO_PORT1 | DECODE_ENABLE_AUDIO_PORT2
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| DECODE_ENABLE_AUDIO_PORT3 | DECODE_ENABLE_MSS_PORT2
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| DECODE_ENABLE_MSS_PORT3 | DECODE_ENABLE_FDC_PORT0
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| DECODE_ENABLE_FDC_PORT1 | DECODE_ENABLE_GAME_PORT
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| DECODE_ENABLE_KBC_PORT | DECODE_ENABLE_ACPIUC_PORT
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| DECODE_ENABLE_ADLIB_PORT;
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dev = PCI_DEV(0, 0x14, 3);
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/* Serial port numeration on Hudson:
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* PORT0 - 0x3f8
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* PORT1 - 0x2f8
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* PORT5 - 0x2e8
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* PORT7 - 0x3e8
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*/
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tmp = DECODE_ENABLE_SERIAL_PORT0 | DECODE_ENABLE_SERIAL_PORT1
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| DECODE_ENABLE_SERIAL_PORT5 | DECODE_ENABLE_SERIAL_PORT7;
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pci_write_config32(dev, LPC_IO_PORT_DECODE_ENABLE, tmp);
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}
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@ -117,6 +117,10 @@
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#define LPC_ALT_WIDEIO1_ENABLE BIT(2)
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#define LPC_ALT_WIDEIO0_ENABLE BIT(0)
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#define LPC_TRUSTED_PLATFORM_MODULE 0x7c
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#define TPM_12_EN BIT(0)
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#define TPM_LEGACY_EN BIT(2)
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#define LPC_WIDEIO2_GENERIC_PORT 0x90
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#define SPI_CNTRL0 0x00
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