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mainboard/intel/cannonlake_rvp: Enable S0ix 

This patch enables S0ix from the devicetree.

Change-Id: I38662dc7203366bdee5f1c7aaa18979867a79ba1
Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
Reviewed-on: https://review.coreboot.org/25293
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Vaibhav Shankar 2018-03-19 19:04:16 -07:00 committed by Patrick Georgi
parent 2da6ec40bb
commit 8cf149007f
2 changed files with 6 additions and 0 deletions
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3
src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb
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@ -70,6 +70,9 @@ chip soc/intel/cannonlake
# GPIO for SD card detect # GPIO for SD card detect
register "sdcard_cd_gpio" = "GPP_G5" register "sdcard_cd_gpio" = "GPP_G5"
# Enable S0ix
register "s0ix_enable" = "1"
# Audio # Audio
register "i2c[3]" = "{ register "i2c[3]" = "{
.speed = I2C_SPEED_STANDARD, .speed = I2C_SPEED_STANDARD,

3
src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
View File

@ -68,6 +68,9 @@ chip soc/intel/cannonlake
# GPIO for SD card detect # GPIO for SD card detect
register "sdcard_cd_gpio" = "GPP_G5" register "sdcard_cd_gpio" = "GPP_G5"
# Enable S0ix
register "s0ix_enable" = "1"
device domain 0 on device domain 0 on
device pci 00.0 on end # Host Bridge device pci 00.0 on end # Host Bridge
device pci 02.0 on end # Integrated Graphics Device device pci 02.0 on end # Integrated Graphics Device