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Use die() to assure the processor can't wake up from an interrupt. 

Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Stefan Reinauer <stepan@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6224 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Nils Jacobs 2010-12-30 19:21:08 +00:00 committed by Stefan Reinauer
parent f1939bb29b
commit 8cf54c9f23
2 changed files with 3 additions and 5 deletions
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5
src/northbridge/amd/gx2/pll_reset.c
View File

@ -78,9 +78,8 @@ static void pll_reset(void)
} else if (CONFIG_GX2_PROCESSOR_MHZ == 300) { } else if (CONFIG_GX2_PROCESSOR_MHZ == 300) {
DEFAULT_FBDIV = 18; DEFAULT_FBDIV = 18;
} else { } else {
printk(BIOS_ERR, "Unsupported GX2_PROCESSOR_MHZ setting!\n");
post_code(POST_PLL_CPU_VER_FAIL); post_code(POST_PLL_CPU_VER_FAIL);
__asm__ __volatile__("hlt\n"); die("Unsupported GX2_PROCESSOR_MHZ setting!\n");
} }
/* clear the Bypass bit */ /* clear the Bypass bit */
@ -186,7 +185,7 @@ static void pll_reset(void)
/* You should never get here..... The chip has reset. */ /* You should never get here..... The chip has reset. */
post_code(POST_PLL_RESET_FAIL); post_code(POST_PLL_RESET_FAIL);
while (1); die("CONFIGURING PLL FAILURE\n");
} /* we haven't configured the PLL; do it now */ } /* we haven't configured the PLL; do it now */

3
src/northbridge/amd/lx/pll_reset.c
View File

@ -59,9 +59,8 @@ static void pll_reset(char manualconf)
wrmsr(GLCP_SYS_RSTPLL, msrGlcpSysRstpll); wrmsr(GLCP_SYS_RSTPLL, msrGlcpSysRstpll);
/* You should never get here..... The chip has reset. */ /* You should never get here..... The chip has reset. */
printk(BIOS_ERR, "CONFIGURING PLL FAILURE\n");
post_code(POST_PLL_RESET_FAIL); post_code(POST_PLL_RESET_FAIL);
__asm__ __volatile__("hlt\n"); die("CONFIGURING PLL FAILURE\n");
} }
printk(BIOS_DEBUG, "PLL configured.\n"); printk(BIOS_DEBUG, "PLL configured.\n");