soc/intel/mtl: Adaptively disable 3-strike error for QS silicon

This patch provides a way to mask the 3-strike error on Intel
Meteor Lake SoC platform across pre-prod and prod SoC.

This patch decouples MSR selection for 3-strike error disablement, ensuring compatibility across SoC types.

Without the correct MSR been programmed the SoC platform is unable to disable 3-strike error.

BUG=b:314883362
TEST=Disable the 3-strike on google/screebo with QS silicon.

Change-Id: I5363102deea67c44c9433a3f66c92badb0d0f182
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79473
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/intel/meteorlake/cpu.c

@@ -142,7 +142,10 @@ void soc_core_init(struct device *cpu)
 
 	if (CONFIG(DROP_CPU_FEATURE_PROGRAM_IN_FSP)) {
 		/* Disable 3-strike error */
-		disable_three_strike_error();
+		if (CONFIG(SOC_INTEL_METEORLAKE_PRE_PRODUCTION_SILICON))
+			disable_three_strike_error();
+		else
+			disable_signaling_three_strike_event();
 
 		set_aesni_lock();