diff --git a/src/mainboard/google/fizz/variants/endeavour/gpio.c b/src/mainboard/google/fizz/variants/endeavour/gpio.c
index 0915c3eb7d..432a180362 100644
--- a/src/mainboard/google/fizz/variants/endeavour/gpio.c
+++ b/src/mainboard/google/fizz/variants/endeavour/gpio.c
@@ -27,9 +27,9 @@ static const struct pad_config gpio_table[] = {
 /* SUSACK# */		PAD_CFG_NC(GPP_A15), /* TP150 */
 /* SD_1P8_SEL */	PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
 /* SD_PWR_EN# */	PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1),
-/* ISH_GP0 */		PAD_CFG_GPI_APIC(GPP_A18, NONE, DEEP), /* 7322_INTO */
+/* ISH_GP0 */		PAD_CFG_GPI_INT(GPP_A18, NONE, PLTRST, LEVEL), /* 7322_INTO */
 /* ISH_GP1 */		PAD_CFG_GPO_GPIO_DRIVER(GPP_A19, 1, DEEP, NONE), /* 7322_OE */
-/* ISH_GP2 */		PAD_CFG_GPI_APIC(GPP_A20, NONE, DEEP), /* 7322_INTO */
+/* ISH_GP2 */		PAD_CFG_GPI_INT(GPP_A20, NONE, PLTRST, LEVEL), /* 7322_INTO */
 /* ISH_GP3 */		PAD_CFG_GPO_GPIO_DRIVER(GPP_A21, 1, DEEP, NONE), /* 7322_OE */
 /* ISH_GP4 */		PAD_CFG_NC(GPP_A22),
 /* ISH_GP5 */		PAD_CFG_NC(GPP_A23),
diff --git a/src/mainboard/google/fizz/variants/endeavour/overridetree.cb b/src/mainboard/google/fizz/variants/endeavour/overridetree.cb
index 861e1b194a..1d837934ac 100644
--- a/src/mainboard/google/fizz/variants/endeavour/overridetree.cb
+++ b/src/mainboard/google/fizz/variants/endeavour/overridetree.cb
@@ -137,7 +137,7 @@ chip soc/intel/skylake
 				register "hid" = "ACPI_DT_NAMESPACE_HID"
 				register "desc" = ""Chrontel 7322""
 				register "uid" = "1"
-				register "compat_string" = ""chrontel,7322""
+				register "compat_string" = ""chrontel,ch7322""
 				register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_HIGH(GPP_A18)"
 				device i2c 75 on end
 			end
@@ -145,7 +145,7 @@ chip soc/intel/skylake
 				register "hid" = "ACPI_DT_NAMESPACE_HID"
 				register "desc" = ""Chrontel 7322""
 				register "uid" = "2"
-				register "compat_string" = ""chrontel,7322""
+				register "compat_string" = ""chrontel,ch7322""
 				register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_HIGH(GPP_A20)"
 				device i2c 76 on end
 			end