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soc/intel/meteorlake: Set TCC to 90°C 

Set tcc_offset value to 20 in chipset for Thermal Control
Circuit (TCC) activation feature for meteorlake silicon.
Also, remove tcc_offset default value from rex baseboard
and variants.

BUG=b:270664854
BRANCH=None
TEST=Build FW and test on rex board

Change-Id: Ieec1b7e0873eef46a56e612ed1d9445019b1f4a9
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76232
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit is contained in:
Sumeet Pawnikar 2023-07-04 10:23:58 +05:30 committed by Felix Held
parent 969a2a9a30
commit 8d0a063810
3 changed files with 3 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb
View File

@ -36,9 +36,6 @@ chip soc/intel/meteorlake
# DPTF enable # DPTF enable
register "dptf_enable" = "1" register "dptf_enable" = "1"
# Temporary setting TCC of 90C = Tj max (110) - TCC_Offset (20)
register "tcc_offset" = "20"
# Enable CNVi BT # Enable CNVi BT
register "cnvi_bt_core" = "true" register "cnvi_bt_core" = "true"

3
src/mainboard/google/rex/variants/screebo/overridetree.cb
View File

@ -64,9 +64,6 @@ chip soc/intel/meteorlake
[PchSerialIoIndexI2C5] = PchSerialIoPci, [PchSerialIoIndexI2C5] = PchSerialIoPci,
}" }"
# Temporary setting TCC of 90C = Tj max - Tcc
register "tcc_offset" = "20"
# Intel Common SoC Config # Intel Common SoC Config
#+-------------------+---------------------------+ #+-------------------+---------------------------+
#| Field | Value | #| Field | Value |

3
src/soc/intel/meteorlake/chipset.cb
View File

@ -19,6 +19,9 @@ chip soc/intel/meteorlake
# putting it under register "common_soc_config" in overridetree.cb file. # putting it under register "common_soc_config" in overridetree.cb file.
register "common_soc_config.pch_thermal_trip" = "130" register "common_soc_config.pch_thermal_trip" = "130"
# Temporary setting TCC of 90C = Tj max (110) - TCC_Offset (20)
register "tcc_offset" = "20"
# Enable CNVi WiFi # Enable CNVi WiFi
register "cnvi_wifi_core" = "true" register "cnvi_wifi_core" = "true"