soc/rockchip: Fix typos
Change-Id: I85ccb9e1458340bd5bc2a0eb9abed8d0eeb2fe65 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39028 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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@ -135,7 +135,7 @@ static void rk_edp_init_analog_func(struct rk_edp *edp)
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static void rk_edp_init_aux(struct rk_edp *edp)
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{
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/* Clear inerrupts related to AUX channel */
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/* Clear interrupts related to AUX channel */
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write32(&edp->regs->dp_int_sta, AUX_FUNC_EN_N);
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/* Disable AUX channel module */
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@ -733,7 +733,7 @@ static int hdmi_read_edid(int block, u8 *buff)
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u32 trytime = 5;
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u32 n, j, val;
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/* set ddc i2c clk which devided from ddc_clk to 100khz */
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/* set ddc i2c clk which derived from ddc_clk to 100kHz */
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write32(&hdmi_regs->i2cm_ss_scl_hcnt_0_addr, 0x7a);
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write32(&hdmi_regs->i2cm_ss_scl_lcnt_0_addr, 0x8d);
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clrsetbits32(&hdmi_regs->i2cm_div, HDMI_I2CM_DIV_FAST_STD_MODE,
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@ -100,7 +100,7 @@ void tsadc_init(void)
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/*
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tsadc iomux must be set after the tshut polarity setting,
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since the tshut polarity defalut low active,
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since the tshut polarity default low active,
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so if you enable tsadc iomux,it will output high
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*/
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setbits32(&rk3288_pmu->iomux_tsadc_int, IOMUX_TSADC_INT);
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@ -304,7 +304,7 @@ static void rkclk_set_pll(u32 *pll_con, const struct pll_div *div)
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u32 output_khz = vco_khz / div->postdiv1 / div->postdiv2;
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printk(BIOS_DEBUG, "PLL at %p: fbdiv=%d, refdiv=%d, postdiv1=%d, "
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"postdiv2=%d, vco=%u khz, output=%u khz\n",
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"postdiv2=%d, vco=%u kHz, output=%u kHz\n",
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pll_con, div->fbdiv, div->refdiv, div->postdiv1,
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div->postdiv2, vco_khz, output_khz);
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assert(vco_khz >= VCO_MIN_KHZ && vco_khz <= VCO_MAX_KHZ &&
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@ -485,7 +485,7 @@ void rkclk_init(void)
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/* some cru registers changed by bootrom, we'd better reset them to
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* reset/default values described in TRM to avoid confusion in kernel.
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* Please consider these threee lines as a fix of bootrom bug.
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* Please consider these three lines as a fix of bootrom bug.
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*/
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write32(&cru_ptr->clksel_con[12], 0xffff4101);
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write32(&cru_ptr->clksel_con[19], 0xffff033f);
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@ -319,7 +319,7 @@ static int rk_mipi_dsi_get_lane_bps(struct rk_mipi_dsi *dsi,
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min_prediv = DIV_ROUND_UP(fref, 40 * MHz);
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max_prediv = fref / (5 * MHz);
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/* constraint: 80MHz <= Fvco <= 1500Mhz */
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/* constraint: 80MHz <= Fvco <= 1500MHz */
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fvco_min = 80 * MHz;
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fvco_max = 1500 * MHz;
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min_delta = 1500 * MHz;
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@ -112,7 +112,7 @@ void tsadc_init(uint32_t polarity)
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/* setup the automatic mode:
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* AUTO_PERIOD: interleave between every two accessing of TSADC
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* AUTO_DEBOUNCE: only generate interrupt or TSHUT when temprature
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* AUTO_DEBOUNCE: only generate interrupt or TSHUT when temperature
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* is higher than COMP_INT for "debounce" times
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* AUTO_PERIOD_HT: the interleave between every two accessing after the
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* temperature is higher than COMP_SHUT or COMP_INT
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@ -123,7 +123,7 @@ void tsadc_init(uint32_t polarity)
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write32(&rk3399_tsadc->hight_int_debounce, AUTO_DEBOUNCE);
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write32(&rk3399_tsadc->auto_period_ht, AUTO_PERIOD_HT);
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write32(&rk3399_tsadc->hight_tshut_debounce, AUTO_DEBOUNCE_HT);
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/* Enable the src0, negative temprature coefficient */
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/* Enable the src0, negative temperature coefficient */
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setbits32(&rk3399_tsadc->auto_con, Q_SEL | SRC0_EN);
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udelay(100);
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setbits32(&rk3399_tsadc->auto_con, AUTO_EN);
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