soc/rockchip: Fix typos

Change-Id: I85ccb9e1458340bd5bc2a0eb9abed8d0eeb2fe65
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39028
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Elyes HAOUAS 2020-02-20 18:20:57 +01:00 committed by Patrick Georgi
parent 23e3f9d6ed
commit 8d1b0f1dbd
6 changed files with 8 additions and 8 deletions

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@ -135,7 +135,7 @@ static void rk_edp_init_analog_func(struct rk_edp *edp)
static void rk_edp_init_aux(struct rk_edp *edp)
{
/* Clear inerrupts related to AUX channel */
/* Clear interrupts related to AUX channel */
write32(&edp->regs->dp_int_sta, AUX_FUNC_EN_N);
/* Disable AUX channel module */

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@ -733,7 +733,7 @@ static int hdmi_read_edid(int block, u8 *buff)
u32 trytime = 5;
u32 n, j, val;
/* set ddc i2c clk which devided from ddc_clk to 100khz */
/* set ddc i2c clk which derived from ddc_clk to 100kHz */
write32(&hdmi_regs->i2cm_ss_scl_hcnt_0_addr, 0x7a);
write32(&hdmi_regs->i2cm_ss_scl_lcnt_0_addr, 0x8d);
clrsetbits32(&hdmi_regs->i2cm_div, HDMI_I2CM_DIV_FAST_STD_MODE,

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@ -100,7 +100,7 @@ void tsadc_init(void)
/*
tsadc iomux must be set after the tshut polarity setting,
since the tshut polarity defalut low active,
since the tshut polarity default low active,
so if you enable tsadc iomux,it will output high
*/
setbits32(&rk3288_pmu->iomux_tsadc_int, IOMUX_TSADC_INT);

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@ -304,7 +304,7 @@ static void rkclk_set_pll(u32 *pll_con, const struct pll_div *div)
u32 output_khz = vco_khz / div->postdiv1 / div->postdiv2;
printk(BIOS_DEBUG, "PLL at %p: fbdiv=%d, refdiv=%d, postdiv1=%d, "
"postdiv2=%d, vco=%u khz, output=%u khz\n",
"postdiv2=%d, vco=%u kHz, output=%u kHz\n",
pll_con, div->fbdiv, div->refdiv, div->postdiv1,
div->postdiv2, vco_khz, output_khz);
assert(vco_khz >= VCO_MIN_KHZ && vco_khz <= VCO_MAX_KHZ &&
@ -485,7 +485,7 @@ void rkclk_init(void)
/* some cru registers changed by bootrom, we'd better reset them to
* reset/default values described in TRM to avoid confusion in kernel.
* Please consider these threee lines as a fix of bootrom bug.
* Please consider these three lines as a fix of bootrom bug.
*/
write32(&cru_ptr->clksel_con[12], 0xffff4101);
write32(&cru_ptr->clksel_con[19], 0xffff033f);

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@ -319,7 +319,7 @@ static int rk_mipi_dsi_get_lane_bps(struct rk_mipi_dsi *dsi,
min_prediv = DIV_ROUND_UP(fref, 40 * MHz);
max_prediv = fref / (5 * MHz);
/* constraint: 80MHz <= Fvco <= 1500Mhz */
/* constraint: 80MHz <= Fvco <= 1500MHz */
fvco_min = 80 * MHz;
fvco_max = 1500 * MHz;
min_delta = 1500 * MHz;

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@ -112,7 +112,7 @@ void tsadc_init(uint32_t polarity)
/* setup the automatic mode:
* AUTO_PERIOD: interleave between every two accessing of TSADC
* AUTO_DEBOUNCE: only generate interrupt or TSHUT when temprature
* AUTO_DEBOUNCE: only generate interrupt or TSHUT when temperature
* is higher than COMP_INT for "debounce" times
* AUTO_PERIOD_HT: the interleave between every two accessing after the
* temperature is higher than COMP_SHUT or COMP_INT
@ -123,7 +123,7 @@ void tsadc_init(uint32_t polarity)
write32(&rk3399_tsadc->hight_int_debounce, AUTO_DEBOUNCE);
write32(&rk3399_tsadc->auto_period_ht, AUTO_PERIOD_HT);
write32(&rk3399_tsadc->hight_tshut_debounce, AUTO_DEBOUNCE_HT);
/* Enable the src0, negative temprature coefficient */
/* Enable the src0, negative temperature coefficient */
setbits32(&rk3399_tsadc->auto_con, Q_SEL | SRC0_EN);
udelay(100);
setbits32(&rk3399_tsadc->auto_con, AUTO_EN);