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mb/google/zoombini/variants/meowth: enable SAR power 

BUG=b:69011806
BRANCH=master
TEST=none

Change-Id: I2ea44b03336b901af68f9092f3386b42d8516b72
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/24962
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Nick Vaccaro 2018-03-01 16:22:45 -08:00 committed by Martin Roth
parent 6a3891404c
commit 8d23152e69
1 changed files with 1 additions and 1 deletions
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src/mainboard/google/zoombini/variants/meowth/gpio.c
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@ -89,7 +89,7 @@ static const struct pad_config gpio_table[] = {
/* SML0CLK */ PAD_CFG_GPI(GPP_C3, NONE, DEEP), /* PCH_SAR1_INT_L */ /* SML0CLK */ PAD_CFG_GPI(GPP_C3, NONE, DEEP), /* PCH_SAR1_INT_L */
/* SML0DATA */ PAD_CFG_GPI(GPP_C4, NONE, DEEP), /* PCH_SAR0_INT_L */ /* SML0DATA */ PAD_CFG_GPI(GPP_C4, NONE, DEEP), /* PCH_SAR0_INT_L */
/* SML0ALERT# */ PAD_CFG_GPI(GPP_C5, NONE, DEEP), /* GPP_C5_STRAP */ /* SML0ALERT# */ PAD_CFG_GPI(GPP_C5, NONE, DEEP), /* GPP_C5_STRAP */
/* SM1CLK */ PAD_CFG_GPO(GPP_C6, 0, DEEP), /* PCH_SAR_PWR_EN */ /* SM1CLK */ PAD_CFG_GPO(GPP_C6, 1, DEEP), /* PCH_SAR_PWR_EN */
/* SM1DATA */ PAD_NC(GPP_C7, NONE), /* SM1DATA */ PAD_NC(GPP_C7, NONE),
/* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, /* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP,
NF1), /* UART_PCH_RX_DEBUG_TX */ NF1), /* UART_PCH_RX_DEBUG_TX */